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;;; vim: set ft=avr:

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.nolist

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.include "m168def.inc"      ; Same family as 328P

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.list

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.include "macros.inc"

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;; Interrupt Vector

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.cseg

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.org 0x0000

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        rjmp        Main

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;; CPU cycles / second: 16 Mhz

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.set CPU_CYCLES = 16 * 1000 * 1000

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;; Delays

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.include "delay.inc"

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    21

;; DMX baud raite: 250k

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.set DMX_BAUD = 250 * 1000

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;; CPU cycles / bit: 64

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.set DMX_CYCLES = CPU_CYCLES / DMX_BAUD

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    27

;; DMX output I/O

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.set DMX_DDR = DDRB

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.set DMX_PORT = PORTB

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.equ DMX_DATA = PORTB3

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    32

;; DMX protocol timer

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; Registers

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.set DMX_TIMER_CRA = TCCR2A

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.set DMX_TIMER_CRB = TCCR2B

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.set DMX_TIMER_CNT = TCNT2

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.set DMX_TIMER_OCRA = OCR2A

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.set DMX_TIMER_OCRB = OCR2B

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.set DMX_TIMER_IMSK = TIMSK2

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.set DMX_TIMER_IFR = TIFR2

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; Compare output match isn't used

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.set DMX_TIMER_COMA = 0b00

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.set DMX_TIMER_COMB = 0b00

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; Control register, generation mode value

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.set DMX_TIMER_WGM_10 = 0b10        ; CTC

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.set DMX_TIMER_WGM_2 = 0b0

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; Clock select

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.set DMX_TIMER_CS_STOP = 0b000

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.set DMX_TIMER_CS = 0b001      ; 1/1

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;.set DMX_TIMER_CS = 0b111       ; 1/1024

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; Counted value

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.set DMX_TIMER_TOP = DMX_CYCLES     ; number of cycles for baud

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    58

;; Debug LED

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.set LED_DDR = DDRB

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.set LED_PORT = PORTB

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.set LED_PIN = PINB

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.set LED_BIT = PORTB0

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;; Set up DMX output

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DMX_Init:

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    ; Setup output port

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        ; out

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        sbi     DMX_DDR, DMX_DATA

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    70

        ; drive high

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        sbi     DMX_PORT, DMX_DATA

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    73

    ; Setup timer

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        ; setup CTC mode with no output pins

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        poke        [DMX_TIMER_CRA, r16, (DMX_TIMER_COMA << COM2A0) | (DMX_TIMER_COMB << COM2B0) | (DMX_TIMER_WGM_10 << WGM20)]

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        poke        [DMX_TIMER_CRB, r16, (DMX_TIMER_WGM_2 << WGM22) | (DMX_TIMER_CS_STOP << CS20)]

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    78

        ; trigger threshold for CTC

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        poke        [DMX_TIMER_OCRA, r16, (DMX_TIMER_TOP)]

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    81

    ; OK

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    ret

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    84

;; Start Break signal

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;;

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;; 22 bits - 1s long; then DMX_Break_Mark

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;;

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DMX_Break_Start:

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    ; Low

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        cbi         DMX_PORT, DMX_DATA

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    ret

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    94

;; Start Mark-after-break signal

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;;

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;; 2 bits - 1s long; then DMX_Break_End

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;;

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DMX_Break_Mark:

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    ; High

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        sbi         DMX_PORT, DMX_DATA

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   102

    ret

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   104

;; End break; prepare for DMX_Frame

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DMX_Frame_Start:

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    ; Start timer

   107

        poke        [DMX_TIMER_CRB, r20, (DMX_TIMER_WGM_2 << WGM22) | (DMX_TIMER_CS << CS20)]

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   109

    ret

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   111

;; Do a full DMX break, using some random length

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;;

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DMX_Break:

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    ; Break

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        ; start

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        rcall       DMX_Break_Start

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   118

        ; wait; about 100ms?

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        ldi         r20, 82 / 10

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        rcall       VarDelay

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   122

    ; MAB

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        ; mark

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        rcall       DMX_Break_Mark

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   126

        ; short wait

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        ldi         r20, 1

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        rcall       VarDelay

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   130

    ; Timed frames

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        ; start frame

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        rcall       DMX_Frame_Start

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   134

    ; ok

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    ret

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   137

;; Bitbang one DMX bit out

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;;  uses SREG/C to send

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;

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; Uses Timer2 as a bit sync clock, sending out the next bit once we've hit 64 cycles on the timer

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DMX_Bit:

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    ; Wait for bit sync clock

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_dmx_bit_wait:

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        ; test OCA hit

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        sbic    TIFR2, OCF2A     

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        rjmp    _dmx_bit_wait   

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;sbi         LED_PORT, LED_BIT

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    ; Output bit

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        ; XXX: ugly bit-testing, can't we do this using something more nifty?

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        brcs    _dmx_bit_1

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        ; bit 0

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        cbi     DMX_PORT, DMX_DATA

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        rjmp    _dmx_bit_done

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_dmx_bit_1:

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        ; bit 1

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        sbi     DMX_PORT, DMX_DATA

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        nop

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   163

    ; Bit sent

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_dmx_bit_done:

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        ; reset OCA hit for next bit

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        cbi     TIFR2, OCF2A

   167

   168

    ; OK, bit sync clock keeps running for next bit

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    ret

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   171

;; Bitbang one DMX byte out, using DMX_Bit

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;;  r16: byte value

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;

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; Uses Timer2 as a bit sync clock; must call DMX_Frame_Start before first DMX_Frame

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DMX_Frame:

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    ; Start bit

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        clc

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        rcall       DMX_Bit

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    ; Data bits: 8

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        ldi         r21, 8

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_dmx_frame_loop:

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        ; shift + send bit

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        lsl         r16

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        rcall       DMX_Bit

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   188

        ; loop

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        dec         r21

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        brne        _dmx_frame_loop

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   192

    ; Stop bits

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        sec

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        rcall       DMX_Bit

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        rcall       DMX_Bit

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    ; OK

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    ret

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;; End of DMX frames

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DMX_Frame_End:

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    ; Keep mark from end of last frame; DMX_Break_Start starts the break

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    ; Stop the timer

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        poke        [DMX_TIMER_CRB, r20, (DMX_TIMER_WGM_2 << WGM22) | (DMX_TIMER_CS_STOP << CS20)]

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   206

    ; OK

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    ret

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;; Send one value on all frames

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;;  r17: byte value

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DMX_Flood:

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    ; Break

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        rcall       DMX_Break

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    ; Start code

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        ldi         r16, 0

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        rcall       DMX_Frame

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    ; Channels

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        ; number of channels to send

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        ldi         r22, 100

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_dmx_flood_channels:

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        ; restore channel value

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        mov         r16, r17

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        ; send channel value

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        rcall       DMX_Frame

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        ; loop

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        dec         r22

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        brne        _dmx_flood_channels

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    ; End packet

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        rcall       DMX_Frame_End

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    ret

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   240

;; Program main

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Main:

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; Initialization

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    ; Debug

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        sbi         LED_DDR, LED_BIT

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sbi         LED_PORT, LED_BIT

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    ; Stack

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		poke		[SPL, r16:r17, RAMEND]

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    ; Init

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        rcall       DMX_Init

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cbi         LED_PORT, LED_BIT

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   255

    ; Send; value

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_main_loop:

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        ldi         r17, 255

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        rcall       DMX_Flood

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cbi         LED_PORT, LED_BIT

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        ; never returns..

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        rjmp        _main_loop

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