arduino: hw.S@5254ba612630 (annotated)

0 0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	1	.nolist
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	2	.include "m168def.inc" ; Same family as 328P
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	3	.list
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	4
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	5	; Interrupt vector
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	6	.org 0x00
0 0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	7	rjmp main ; Reset
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	8
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	9	.org OC1Aaddr
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	10	rjmp timer ; Timer 1 Compare A
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	11
0 0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	12	; Program code
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	13	main:
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	14	; Setup pins for output
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	15	sbi DDRB, PORTB4 ; Out
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	16	sbi DDRB, PORTB5 ; Out
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	17
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	18	; Flags for output
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	19	ldi r16, (1 << PORTB4)
1 e0b8d42c62e1 include m168def.inc with #directives removed Tero Marttila <terom@fixme.fi> parents: 0 diff changeset	20
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	21	; Setup Timer 0
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	22	; Count to 64k
3 0584de343264 SPI/LCD thingie Tero Marttila <terom@fixme.fi> parents: 2 diff changeset	23	ldi r18, HIGH(0xffff/2)
0584de343264 SPI/LCD thingie Tero Marttila <terom@fixme.fi> parents: 2 diff changeset	24	ldi r19, LOW(0xffff/2)
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	25	sts OCR1AH, r18
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	26	sts OCR1AL, r19
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	27
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	28	; Normal port operation for both comperators
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	29	; Bits WGM10:1 zero
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	30	ldi r18, 0x00
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	31	sts TCCR1A, r18
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	32
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	33	; CTC mode, 1/64 prescaled
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	34	; the timer will start counting from now, but that shouldn't matter..
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	35	ldi r18, (1 << WGM12) \| (0b011 << CS10)
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	36	sts TCCR1B, r18
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	37
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	38	; Enable timer interrupt
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	39	ldi r18, (1 << OCIE1A)
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	40	sts TIMSK1, r18
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	41
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	42	; Setup sleep for Idle mode
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	43	ldi r18, (0b000 << SM0) \| (1 << SE)
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	44	sts SMCR, r18
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	45
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	46	; ...and enable interrupts
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	47	sei
0 0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	48
0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	49	loop:
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	50	; Flip
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	51	com r16
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	52
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	53	; Output
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	54	out PORTB, r16
0 0fa52c10196e My First Assembler Tero Marttila <terom@fixme.fi> parents: diff changeset	55
2 f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	56	; Wait
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	57	wait: sleep
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	58	cpi r20, 1
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	59	brne wait
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	60	ldi r20, 0
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	61
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	62	; continue
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	63	rjmp loop
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	64
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	65	; Counter overflow handler
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	66	timer:
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	67	; Set flag
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	68	ldi r20, 1
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	69
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	70	; Re-enable interrupts
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	71	reti
f7bdcc9806e6 16-bit timer blink\! Tero Marttila <terom@fixme.fi> parents: 1 diff changeset	72

author	Tero Marttila <terom@paivola.fi>
	Sun, 20 Apr 2014 23:51:57 +0300
changeset 80	5254ba612630
parent 3	0584de343264
permissions	-rw-r--r--