1

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************

     2

;***** Created: 2005-01-11 10:30 ******* Source: ATmega168.xml ***********

     3

;*************************************************************************

     4

;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y

     5

;* 

     6

;* Number            : AVR000

     7

;* File Name         : "m168def.inc"

     8

;* Title             : Register/Bit Definitions for the ATmega168

     9

;* Date              : 2005-01-11

    10

;* Version           : 2.14

    11

;* Support E-mail    : avr@atmel.com

    12

;* Target MCU        : ATmega168

    13

;* 

    14

;* DESCRIPTION

    15

;* When including this file in the assembly program file, all I/O register 

    16

;* names and I/O register bit names appearing in the data book can be used.

    17

;* In addition, the six registers forming the three data pointers X, Y and 

    18

;* Z have been assigned names XL - ZH. Highest RAM address for Internal 

    19

;* SRAM is also defined 

    20

;* 

    21

;* The Register names are represented by their hexadecimal address.

    22

;* 

    23

;* The Register Bit names are represented by their bit number (0-7).

    24

;* 

    25

;* Please observe the difference in using the bit names with instructions

    26

;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"

    27

;* (skip if bit in register set/cleared). The following example illustrates

    28

;* this:

    29

;* 

    30

;* in    r16,PORTB             ;read PORTB latch

    31

;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)

    32

;* out   PORTB,r16             ;output to PORTB

    33

;* 

    34

;* in    r16,TIFR              ;read the Timer Interrupt Flag Register

    35

;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)

    36

;* rjmp  TOV0_is_set           ;jump if set

    37

;* ...                         ;otherwise do something else

    38

;*************************************************************************

    39

    40

; #ifndef _M168DEF_INC_

    41

; #define _M168DEF_INC_

    42

    43

    44

; #pragma partinc 0

    45

    46

; ***** SPECIFY DEVICE ***************************************************

    47

.device ATmega168

    48

; #pragma AVRPART ADMIN PART_NAME ATmega168

    49

.equ	SIGNATURE_000	= 0x1e

    50

.equ	SIGNATURE_001	= 0x94

    51

.equ	SIGNATURE_002	= 0x06

    52

    53

; #pragma AVRPART CORE CORE_VERSION V2E

    54

    55

    56

; ***** I/O REGISTER DEFINITIONS *****************************************

    57

; NOTE:

    58

; Definitions marked "MEMORY MAPPED"are extended I/O ports

    59

; and cannot be used with IN/OUT instructions

    60

.equ	UDR0	= 0xc6	; MEMORY MAPPED

    61

.equ	UBRR0H	= 0xc5	; MEMORY MAPPED

    62

.equ	UBRR0L	= 0xc4	; MEMORY MAPPED

    63

.equ	UCSR0C	= 0xc2	; MEMORY MAPPED

    64

.equ	UCSR0B	= 0xc1	; MEMORY MAPPED

    65

.equ	UCSR0A	= 0xc0	; MEMORY MAPPED

    66

.equ	TWAMR	= 0xbd	; MEMORY MAPPED

    67

.equ	TWCR	= 0xbc	; MEMORY MAPPED

    68

.equ	TWDR	= 0xbb	; MEMORY MAPPED

    69

.equ	TWAR	= 0xba	; MEMORY MAPPED

    70

.equ	TWSR	= 0xb9	; MEMORY MAPPED

    71

.equ	TWBR	= 0xb8	; MEMORY MAPPED

    72

.equ	ASSR	= 0xb6	; MEMORY MAPPED

    73

.equ	OCR2B	= 0xb4	; MEMORY MAPPED

    74

.equ	OCR2A	= 0xb3	; MEMORY MAPPED

    75

.equ	TCNT2	= 0xb2	; MEMORY MAPPED

    76

.equ	TCCR2B	= 0xb1	; MEMORY MAPPED

    77

.equ	TCCR2A	= 0xb0	; MEMORY MAPPED

    78

.equ	OCR1BH	= 0x8b	; MEMORY MAPPED

    79

.equ	OCR1BL	= 0x8a	; MEMORY MAPPED

    80

.equ	OCR1AH	= 0x89	; MEMORY MAPPED

    81

.equ	OCR1AL	= 0x88	; MEMORY MAPPED

    82

.equ	ICR1H	= 0x87	; MEMORY MAPPED

    83

.equ	ICR1L	= 0x86	; MEMORY MAPPED

    84

.equ	TCNT1H	= 0x85	; MEMORY MAPPED

    85

.equ	TCNT1L	= 0x84	; MEMORY MAPPED

    86

.equ	TCCR1C	= 0x82	; MEMORY MAPPED

    87

.equ	TCCR1B	= 0x81	; MEMORY MAPPED

    88

.equ	TCCR1A	= 0x80	; MEMORY MAPPED

    89

.equ	DIDR1	= 0x7f	; MEMORY MAPPED

    90

.equ	DIDR0	= 0x7e	; MEMORY MAPPED

    91

.equ	ADMUX	= 0x7c	; MEMORY MAPPED

    92

.equ	ADCSRB	= 0x7b	; MEMORY MAPPED

    93

.equ	ADCSRA	= 0x7a	; MEMORY MAPPED

    94

.equ	ADCH	= 0x79	; MEMORY MAPPED

    95

.equ	ADCL	= 0x78	; MEMORY MAPPED

    96

.equ	TIMSK2	= 0x70	; MEMORY MAPPED

    97

.equ	TIMSK1	= 0x6f	; MEMORY MAPPED

    98

.equ	TIMSK0	= 0x6e	; MEMORY MAPPED

    99

.equ	PCMSK2	= 0x6d	; MEMORY MAPPED

   100

.equ	PCMSK1	= 0x6c	; MEMORY MAPPED

   101

.equ	PCMSK0	= 0x6b	; MEMORY MAPPED

   102

.equ	EICRA	= 0x69	; MEMORY MAPPED

   103

.equ	PCICR	= 0x68	; MEMORY MAPPED

   104

.equ	OSCCAL	= 0x66	; MEMORY MAPPED

   105

.equ	PRR	= 0x64	; MEMORY MAPPED

   106

.equ	CLKPR	= 0x61	; MEMORY MAPPED

   107

.equ	WDTCSR	= 0x60	; MEMORY MAPPED

   108

.equ	SREG	= 0x3f

   109

.equ	SPH	= 0x3e

   110

.equ	SPL	= 0x3d

   111

.equ	SPMCSR	= 0x37

   112

.equ	MCUCR	= 0x35

   113

.equ	MCUSR	= 0x34

   114

.equ	SMCR	= 0x33

   115

.equ	ACSR	= 0x30

   116

.equ	SPDR	= 0x2e

   117

.equ	SPSR	= 0x2d

   118

.equ	SPCR	= 0x2c

   119

.equ	GPIOR2	= 0x2b

   120

.equ	GPIOR1	= 0x2a

   121

.equ	OCR0B	= 0x28

   122

.equ	OCR0A	= 0x27

   123

.equ	TCNT0	= 0x26

   124

.equ	TCCR0B	= 0x25

   125

.equ	TCCR0A	= 0x24

   126

.equ	GTCCR	= 0x23

   127

.equ	EEARH	= 0x22

   128

.equ	EEARL	= 0x21

   129

.equ	EEDR	= 0x20

   130

.equ	EECR	= 0x1f

   131

.equ	GPIOR0	= 0x1e

   132

.equ	EIMSK	= 0x1d

   133

.equ	EIFR	= 0x1c

   134

.equ	PCIFR	= 0x1b

   135

.equ	TIFR2	= 0x17

   136

.equ	TIFR1	= 0x16

   137

.equ	TIFR0	= 0x15

   138

.equ	PORTD	= 0x0b

   139

.equ	DDRD	= 0x0a

   140

.equ	PIND	= 0x09

   141

.equ	PORTC	= 0x08

   142

.equ	DDRC	= 0x07

   143

.equ	PINC	= 0x06

   144

.equ	PORTB	= 0x05

   145

.equ	DDRB	= 0x04

   146

.equ	PINB	= 0x03

   147

   148

   149

; ***** BIT DEFINITIONS **************************************************

   150

   151

; ***** USART0 ***********************

   152

; UDR0 - USART I/O Data Register

   153

.equ	UDR0_0	= 0	; USART I/O Data Register bit 0

   154

.equ	UDR0_1	= 1	; USART I/O Data Register bit 1

   155

.equ	UDR0_2	= 2	; USART I/O Data Register bit 2

   156

.equ	UDR0_3	= 3	; USART I/O Data Register bit 3

   157

.equ	UDR0_4	= 4	; USART I/O Data Register bit 4

   158

.equ	UDR0_5	= 5	; USART I/O Data Register bit 5

   159

.equ	UDR0_6	= 6	; USART I/O Data Register bit 6

   160

.equ	UDR0_7	= 7	; USART I/O Data Register bit 7

   161

   162

; UCSR0A - USART Control and Status Register A

   163

.equ	MPCM0	= 0	; Multi-processor Communication Mode

   164

.equ	U2X0	= 1	; Double the USART transmission speed

   165

.equ	UPE0	= 2	; Parity Error

   166

.equ	DOR0	= 3	; Data overRun

   167

.equ	FE0	= 4	; Framing Error

   168

.equ	UDRE0	= 5	; USART Data Register Empty

   169

.equ	TXC0	= 6	; USART Transmitt Complete

   170

.equ	RXC0	= 7	; USART Receive Complete

   171

   172

; UCSR0B - USART Control and Status Register B

   173

.equ	TXB80	= 0	; Transmit Data Bit 8

   174

.equ	RXB80	= 1	; Receive Data Bit 8

   175

.equ	UCSZ02	= 2	; Character Size

   176

.equ	TXEN0	= 3	; Transmitter Enable

   177

.equ	RXEN0	= 4	; Receiver Enable

   178

.equ	UDRIE0	= 5	; USART Data register Empty Interrupt Enable

   179

.equ	TXCIE0	= 6	; TX Complete Interrupt Enable

   180

.equ	RXCIE0	= 7	; RX Complete Interrupt Enable

   181

   182

; UCSR0C - USART Control and Status Register C

   183

.equ	UCPOL0	= 0	; Clock Polarity

   184

.equ	UCSZ00	= 1	; Character Size

   185

.equ	UCPHA0	= UCSZ00	; For compatibility

   186

.equ	UCSZ01	= 2	; Character Size

   187

.equ	UDORD0	= UCSZ01	; For compatibility

   188

.equ	USBS0	= 3	; Stop Bit Select

   189

.equ	UPM00	= 4	; Parity Mode Bit 0

   190

.equ	UPM01	= 5	; Parity Mode Bit 1

   191

.equ	UMSEL00	= 6	; USART Mode Select

   192

.equ	UMSEL0	= UMSEL00	; For compatibility

   193

.equ	UMSEL01	= 7	; USART Mode Select

   194

.equ	UMSEL1	= UMSEL01	; For compatibility

   195

   196

   197

; ***** TWI **************************

   198

; TWAMR - TWI (Slave) Address Mask Register

   199

.equ	TWAM0	= 1	; 

   200

.equ	TWAMR0	= TWAM0	; For compatibility

   201

.equ	TWAM1	= 2	; 

   202

.equ	TWAMR1	= TWAM1	; For compatibility

   203

.equ	TWAM2	= 3	; 

   204

.equ	TWAMR2	= TWAM2	; For compatibility

   205

.equ	TWAM3	= 4	; 

   206

.equ	TWAMR3	= TWAM3	; For compatibility

   207

.equ	TWAM4	= 5	; 

   208

.equ	TWAMR4	= TWAM4	; For compatibility

   209

.equ	TWAM5	= 6	; 

   210

.equ	TWAMR5	= TWAM5	; For compatibility

   211

.equ	TWAM6	= 7	; 

   212

.equ	TWAMR6	= TWAM6	; For compatibility

   213

   214

; TWBR - TWI Bit Rate register

   215

.equ	TWBR0	= 0	; 

   216

.equ	TWBR1	= 1	; 

   217

.equ	TWBR2	= 2	; 

   218

.equ	TWBR3	= 3	; 

   219

.equ	TWBR4	= 4	; 

   220

.equ	TWBR5	= 5	; 

   221

.equ	TWBR6	= 6	; 

   222

.equ	TWBR7	= 7	; 

   223

   224

; TWCR - TWI Control Register

   225

.equ	TWIE	= 0	; TWI Interrupt Enable

   226

.equ	TWEN	= 2	; TWI Enable Bit

   227

.equ	TWWC	= 3	; TWI Write Collition Flag

   228

.equ	TWSTO	= 4	; TWI Stop Condition Bit

   229

.equ	TWSTA	= 5	; TWI Start Condition Bit

   230

.equ	TWEA	= 6	; TWI Enable Acknowledge Bit

   231

.equ	TWINT	= 7	; TWI Interrupt Flag

   232

   233

; TWSR - TWI Status Register

   234

.equ	TWPS0	= 0	; TWI Prescaler

   235

.equ	TWPS1	= 1	; TWI Prescaler

   236

.equ	TWS3	= 3	; TWI Status

   237

.equ	TWS4	= 4	; TWI Status

   238

.equ	TWS5	= 5	; TWI Status

   239

.equ	TWS6	= 6	; TWI Status

   240

.equ	TWS7	= 7	; TWI Status

   241

   242

; TWDR - TWI Data register

   243

.equ	TWD0	= 0	; TWI Data Register Bit 0

   244

.equ	TWD1	= 1	; TWI Data Register Bit 1

   245

.equ	TWD2	= 2	; TWI Data Register Bit 2

   246

.equ	TWD3	= 3	; TWI Data Register Bit 3

   247

.equ	TWD4	= 4	; TWI Data Register Bit 4

   248

.equ	TWD5	= 5	; TWI Data Register Bit 5

   249

.equ	TWD6	= 6	; TWI Data Register Bit 6

   250

.equ	TWD7	= 7	; TWI Data Register Bit 7

   251

   252

; TWAR - TWI (Slave) Address register

   253

.equ	TWGCE	= 0	; TWI General Call Recognition Enable Bit

   254

.equ	TWA0	= 1	; TWI (Slave) Address register Bit 0

   255

.equ	TWA1	= 2	; TWI (Slave) Address register Bit 1

   256

.equ	TWA2	= 3	; TWI (Slave) Address register Bit 2

   257

.equ	TWA3	= 4	; TWI (Slave) Address register Bit 3

   258

.equ	TWA4	= 5	; TWI (Slave) Address register Bit 4

   259

.equ	TWA5	= 6	; TWI (Slave) Address register Bit 5

   260

.equ	TWA6	= 7	; TWI (Slave) Address register Bit 6

   261

   262

   263

; ***** TIMER_COUNTER_1 **************

   264

; TIMSK1 - Timer/Counter Interrupt Mask Register

   265

.equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable

   266

.equ	OCIE1A	= 1	; Timer/Counter1 Output CompareA Match Interrupt Enable

   267

.equ	OCIE1B	= 2	; Timer/Counter1 Output CompareB Match Interrupt Enable

   268

.equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable

   269

   270

; TIFR1 - Timer/Counter Interrupt Flag register

   271

.equ	TOV1	= 0	; Timer/Counter1 Overflow Flag

   272

.equ	OCF1A	= 1	; Output Compare Flag 1A

   273

.equ	OCF1B	= 2	; Output Compare Flag 1B

   274

.equ	ICF1	= 5	; Input Capture Flag 1

   275

   276

; TCCR1A - Timer/Counter1 Control Register A

   277

.equ	WGM10	= 0	; Waveform Generation Mode

   278

.equ	WGM11	= 1	; Waveform Generation Mode

   279

.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0

   280

.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1

   281

.equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0

   282

.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1

   283

   284

; TCCR1B - Timer/Counter1 Control Register B

   285

.equ	CS10	= 0	; Prescaler source of Timer/Counter 1

   286

.equ	CS11	= 1	; Prescaler source of Timer/Counter 1

   287

.equ	CS12	= 2	; Prescaler source of Timer/Counter 1

   288

.equ	WGM12	= 3	; Waveform Generation Mode

   289

.equ	WGM13	= 4	; Waveform Generation Mode

   290

.equ	ICES1	= 6	; Input Capture 1 Edge Select

   291

.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler

   292

   293

; TCCR1C - Timer/Counter1 Control Register C

   294

.equ	FOC1B	= 6	; 

   295

.equ	FOC1A	= 7	; 

   296

   297

; GTCCR - General Timer/Counter Control Register

   298

.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0

   299

.equ	TSM	= 7	; Timer/Counter Synchronization Mode

   300

   301

   302

; ***** TIMER_COUNTER_2 **************

   303

; TIMSK2 - Timer/Counter Interrupt Mask register

   304

.equ	TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable

   305

.equ	TOIE2A	= TOIE2	; For compatibility

   306

.equ	OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable

   307

.equ	OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable

   308

   309

; TIFR2 - Timer/Counter Interrupt Flag Register

   310

.equ	TOV2	= 0	; Timer/Counter2 Overflow Flag

   311

.equ	OCF2A	= 1	; Output Compare Flag 2A

   312

.equ	OCF2B	= 2	; Output Compare Flag 2B

   313

   314

; TCCR2A - Timer/Counter2 Control Register A

   315

.equ	WGM20	= 0	; Waveform Genration Mode

   316

.equ	WGM21	= 1	; Waveform Genration Mode

   317

.equ	COM2B0	= 4	; Compare Output Mode bit 0

   318

.equ	COM2B1	= 5	; Compare Output Mode bit 1

   319

.equ	COM2A0	= 6	; Compare Output Mode bit 1

   320

.equ	COM2A1	= 7	; Compare Output Mode bit 1

   321

   322

; TCCR2B - Timer/Counter2 Control Register B

   323

.equ	CS20	= 0	; Clock Select bit 0

   324

.equ	CS21	= 1	; Clock Select bit 1

   325

.equ	CS22	= 2	; Clock Select bit 2

   326

.equ	WGM22	= 3	; Waveform Generation Mode

   327

.equ	FOC2B	= 6	; Force Output Compare B

   328

.equ	FOC2A	= 7	; Force Output Compare A

   329

   330

; TCNT2 - Timer/Counter2

   331

.equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0

   332

.equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1

   333

.equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2

   334

.equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3

   335

.equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4

   336

.equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5

   337

.equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6

   338

.equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7

   339

   340

; OCR2A - Timer/Counter2 Output Compare Register A

   341

.equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0

   342

.equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1

   343

.equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2

   344

.equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3

   345

.equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4

   346

.equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5

   347

.equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6

   348

.equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7

   349

   350

; OCR2B - Timer/Counter2 Output Compare Register B

   351

;.equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0

   352

;.equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1

   353

;.equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2

   354

;.equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3

   355

;.equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4

   356

;.equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5

   357

;.equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6

   358

;.equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7

   359

   360

; ASSR - Asynchronous Status Register

   361

.equ	TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy

   362

.equ	TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy

   363

.equ	OCR2BUB	= 2	; Output Compare Register 2 Update Busy

   364

.equ	OCR2AUB	= 3	; Output Compare Register2 Update Busy

   365

.equ	TCN2UB	= 4	; Timer/Counter2 Update Busy

   366

.equ	AS2	= 5	; Asynchronous Timer/Counter2

   367

.equ	EXCLK	= 6	; Enable External Clock Input

   368

   369

; GTCCR - General Timer Counter Control register

   370

.equ	PSRASY	= 1	; Prescaler Reset Timer/Counter2

   371

.equ	PSR2	= PSRASY	; For compatibility

   372

;.equ	TSM	= 7	; Timer/Counter Synchronization Mode

   373

   374

   375

; ***** AD_CONVERTER *****************

   376

; ADMUX - The ADC multiplexer Selection Register

   377

.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits

   378

.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits

   379

.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits

   380

.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits

   381

.equ	ADLAR	= 5	; Left Adjust Result

   382

.equ	REFS0	= 6	; Reference Selection Bit 0

   383

.equ	REFS1	= 7	; Reference Selection Bit 1

   384

   385

; ADCSRA - The ADC Control and Status register A

   386

.equ	ADPS0	= 0	; ADC  Prescaler Select Bits

   387

.equ	ADPS1	= 1	; ADC  Prescaler Select Bits

   388

.equ	ADPS2	= 2	; ADC  Prescaler Select Bits

   389

.equ	ADIE	= 3	; ADC Interrupt Enable

   390

.equ	ADIF	= 4	; ADC Interrupt Flag

   391

.equ	ADATE	= 5	; ADC  Auto Trigger Enable

   392

.equ	ADSC	= 6	; ADC Start Conversion

   393

.equ	ADEN	= 7	; ADC Enable

   394

   395

; ADCSRB - The ADC Control and Status register B

   396

.equ	ADTS0	= 0	; ADC Auto Trigger Source bit 0

   397

.equ	ADTS1	= 1	; ADC Auto Trigger Source bit 1

   398

.equ	ADTS2	= 2	; ADC Auto Trigger Source bit 2

   399

.equ	ACME	= 6	; 

   400

   401

; ADCH - ADC Data Register High Byte

   402

.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0

   403

.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1

   404

.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2

   405

.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3

   406

.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4

   407

.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5

   408

.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6

   409

.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7

   410

   411

; ADCL - ADC Data Register Low Byte

   412

.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0

   413

.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1

   414

.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2

   415

.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3

   416

.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4

   417

.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5

   418

.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6

   419

.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7

   420

   421

; DIDR0 - Digital Input Disable Register

   422

.equ	ADC0D	= 0	; 

   423

.equ	ADC1D	= 1	; 

   424

.equ	ADC2D	= 2	; 

   425

.equ	ADC3D	= 3	; 

   426

.equ	ADC4D	= 4	; 

   427

.equ	ADC5D	= 5	; 

   428

   429

   430

; ***** ANALOG_COMPARATOR ************

   431

; ACSR - Analog Comparator Control And Status Register

   432

.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0

   433

.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1

   434

.equ	ACIC	= 2	; 

   435

.equ	ACIE	= 3	; Analog Comparator Interrupt Enable

   436

.equ	ACI	= 4	; Analog Comparator Interrupt Flag

   437

.equ	ACO	= 5	; Analog Compare Output

   438

.equ	ACBG	= 6	; Analog Comparator Bandgap Select

   439

.equ	ACD	= 7	; Analog Comparator Disable

   440

   441

; DIDR1 - Digital Input Disable Register 1

   442

.equ	AIN0D	= 0	; AIN0 Digital Input Disable

   443

.equ	AIN1D	= 1	; AIN1 Digital Input Disable

   444

   445

   446

; ***** PORTB ************************

   447

; PORTB - Port B Data Register

   448

.equ	PORTB0	= 0	; Port B Data Register bit 0

   449

.equ	PB0	= 0	; For compatibility

   450

.equ	PORTB1	= 1	; Port B Data Register bit 1

   451

.equ	PB1	= 1	; For compatibility

   452

.equ	PORTB2	= 2	; Port B Data Register bit 2

   453

.equ	PB2	= 2	; For compatibility

   454

.equ	PORTB3	= 3	; Port B Data Register bit 3

   455

.equ	PB3	= 3	; For compatibility

   456

.equ	PORTB4	= 4	; Port B Data Register bit 4

   457

.equ	PB4	= 4	; For compatibility

   458

.equ	PORTB5	= 5	; Port B Data Register bit 5

   459

.equ	PB5	= 5	; For compatibility

   460

.equ	PORTB6	= 6	; Port B Data Register bit 6

   461

.equ	PB6	= 6	; For compatibility

   462

.equ	PORTB7	= 7	; Port B Data Register bit 7

   463

.equ	PB7	= 7	; For compatibility

   464

   465

; DDRB - Port B Data Direction Register

   466

.equ	DDB0	= 0	; Port B Data Direction Register bit 0

   467

.equ	DDB1	= 1	; Port B Data Direction Register bit 1

   468

.equ	DDB2	= 2	; Port B Data Direction Register bit 2

   469

.equ	DDB3	= 3	; Port B Data Direction Register bit 3

   470

.equ	DDB4	= 4	; Port B Data Direction Register bit 4

   471

.equ	DDB5	= 5	; Port B Data Direction Register bit 5

   472

.equ	DDB6	= 6	; Port B Data Direction Register bit 6

   473

.equ	DDB7	= 7	; Port B Data Direction Register bit 7

   474

   475

; PINB - Port B Input Pins

   476

.equ	PINB0	= 0	; Port B Input Pins bit 0

   477

.equ	PINB1	= 1	; Port B Input Pins bit 1

   478

.equ	PINB2	= 2	; Port B Input Pins bit 2

   479

.equ	PINB3	= 3	; Port B Input Pins bit 3

   480

.equ	PINB4	= 4	; Port B Input Pins bit 4

   481

.equ	PINB5	= 5	; Port B Input Pins bit 5

   482

.equ	PINB6	= 6	; Port B Input Pins bit 6

   483

.equ	PINB7	= 7	; Port B Input Pins bit 7

   484

   485

   486

; ***** PORTC ************************

   487

; PORTC - Port C Data Register

   488

.equ	PORTC0	= 0	; Port C Data Register bit 0

   489

.equ	PC0	= 0	; For compatibility

   490

.equ	PORTC1	= 1	; Port C Data Register bit 1

   491

.equ	PC1	= 1	; For compatibility

   492

.equ	PORTC2	= 2	; Port C Data Register bit 2

   493

.equ	PC2	= 2	; For compatibility

   494

.equ	PORTC3	= 3	; Port C Data Register bit 3

   495

.equ	PC3	= 3	; For compatibility

   496

.equ	PORTC4	= 4	; Port C Data Register bit 4

   497

.equ	PC4	= 4	; For compatibility

   498

.equ	PORTC5	= 5	; Port C Data Register bit 5

   499

.equ	PC5	= 5	; For compatibility

   500

.equ	PORTC6	= 6	; Port C Data Register bit 6

   501

.equ	PC6	= 6	; For compatibility

   502

   503

; DDRC - Port C Data Direction Register

   504

.equ	DDC0	= 0	; Port C Data Direction Register bit 0

   505

.equ	DDC1	= 1	; Port C Data Direction Register bit 1

   506

.equ	DDC2	= 2	; Port C Data Direction Register bit 2

   507

.equ	DDC3	= 3	; Port C Data Direction Register bit 3

   508

.equ	DDC4	= 4	; Port C Data Direction Register bit 4

   509

.equ	DDC5	= 5	; Port C Data Direction Register bit 5

   510

.equ	DDC6	= 6	; Port C Data Direction Register bit 6

   511

   512

; PINC - Port C Input Pins

   513

.equ	PINC0	= 0	; Port C Input Pins bit 0

   514

.equ	PINC1	= 1	; Port C Input Pins bit 1

   515

.equ	PINC2	= 2	; Port C Input Pins bit 2

   516

.equ	PINC3	= 3	; Port C Input Pins bit 3

   517

.equ	PINC4	= 4	; Port C Input Pins bit 4

   518

.equ	PINC5	= 5	; Port C Input Pins bit 5

   519

.equ	PINC6	= 6	; Port C Input Pins bit 6

   520

   521

   522

; ***** PORTD ************************

   523

; PORTD - Port D Data Register

   524

.equ	PORTD0	= 0	; Port D Data Register bit 0

   525

.equ	PD0	= 0	; For compatibility

   526

.equ	PORTD1	= 1	; Port D Data Register bit 1

   527

.equ	PD1	= 1	; For compatibility

   528

.equ	PORTD2	= 2	; Port D Data Register bit 2

   529

.equ	PD2	= 2	; For compatibility

   530

.equ	PORTD3	= 3	; Port D Data Register bit 3