terom@12: ;*************************************************************************** 
terom@12: ;* 
terom@12: ;* "div8u" - 8/8 Bit Unsigned Division 
terom@12: ;* 
terom@12: ;* This subroutine divides the two register variables "dd8u" (dividend) and  
terom@12: ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in 
terom@12: ;* "drem8u". 
terom@12: ;*   
terom@12: ;* Number of words	:14 
terom@12: ;* Number of cycles	:97 
terom@12: ;* Low registers used	:1 (drem8u) 
terom@12: ;* High registers used  :3 (dres8u/dd8u,dv8u,dcnt8u) 
terom@12: ;* 
terom@12: ;*************************************************************************** 
terom@12:  
terom@12: ;***** Subroutine Register Variables 
terom@12:  
terom@12: .def	drem8u	=r15		;remainder 
terom@12: .def	dres8u	=r16		;result 
terom@12: .def	dd8u	=r16		;dividend 
terom@12: .def	dv8u	=r17		;divisor 
terom@12: .def	dcnt8u	=r18		;loop counter 
terom@12:  
terom@12: ;***** Code 
terom@12:  
terom@12: div8u:	sub	drem8u,drem8u	;clear remainder and carry 
terom@12: 		ldi	dcnt8u,9		;init loop counter 
terom@12: d8u_1:	rol	dd8u			;shift left dividend 
terom@12: 		dec	dcnt8u			;decrement counter 
terom@12: 		brne	d8u_2		;if done 
terom@12: 		ret					;    return 
terom@12: d8u_2:	rol	drem8u			;shift dividend into remainder 
terom@12: 		sub	drem8u,dv8u		;remainder = remainder - divisor 
terom@12: 		brcc	d8u_3		;if result negative 
terom@12: 		add	drem8u,dv8u		;    restore remainder 
terom@12: 		clc					;    clear carry to be shifted into result 
terom@12: 		rjmp	d8u_1		;else 
terom@12: d8u_3:	sec					;    set carry to be shifted into result 
terom@12: 		rjmp	d8u_1 
terom@12:  
terom@12: