| changeset 4077 | d3022f976946 |
| parent 3997 | 29c77eab14a4 |
| child 4138 | 15f4aa024ad4 |
| 4076:e3ef1c1f149c | 4077:d3022f976946 |
|---|---|
2465 case 0x04: |
2465 case 0x04: |
2466 res = (int32)src1 * (int32)src2; |
2466 res = (int32)src1 * (int32)src2; |
2467 break; |
2467 break; |
2468 |
2468 |
2469 case 0x05: |
2469 case 0x05: |
2470 if ((int32)src2 < 0) |
2470 if ((int32)src2 < 0) { |
2471 res = src1 >> -(int32)src2; |
2471 res = src1 >> -(int32)src2; |
2472 else |
2472 } else { |
2473 res = src1 << src2; |
2473 res = src1 << src2; |
2474 } |
|
2474 break; |
2475 break; |
2475 |
2476 |
2476 case 0x06: |
2477 case 0x06: |
2477 if ((int32)src2 < 0) |
2478 if ((int32)src2 < 0) { |
2478 res = (int32)src1 >> -(int32)src2; |
2479 res = (int32)src1 >> -(int32)src2; |
2479 else |
2480 } else { |
2480 res = (int32)src1 << src2; |
2481 res = (int32)src1 << src2; |
2482 } |
|
2481 break; |
2483 break; |
2482 |
2484 |
2483 case 0x07: /* Bitwise AND */ |
2485 case 0x07: /* Bitwise AND */ |
2484 res = src1 & src2; |
2486 res = src1 & src2; |
2485 break; |
2487 break; |