author | Tero Marttila <terom@paivola.fi> |
Fri, 11 Apr 2014 14:42:10 +0300 | |
changeset 63 | e9b478c817df |
parent 1 | e0b8d42c62e1 |
permissions | -rw-r--r-- |
1
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1 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
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;***** Created: 2005-01-11 10:30 ******* Source: ATmega168.xml *********** |
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;************************************************************************* |
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
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;* |
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include m168def.inc with #directives removed
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;* Number : AVR000 |
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include m168def.inc with #directives removed
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;* File Name : "m168def.inc" |
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;* Title : Register/Bit Definitions for the ATmega168 |
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;* Date : 2005-01-11 |
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include m168def.inc with #directives removed
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;* Version : 2.14 |
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11 |
;* Support E-mail : avr@atmel.com |
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include m168def.inc with #directives removed
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12 |
;* Target MCU : ATmega168 |
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include m168def.inc with #directives removed
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;* |
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;* DESCRIPTION |
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;* When including this file in the assembly program file, all I/O register |
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;* names and I/O register bit names appearing in the data book can be used. |
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include m168def.inc with #directives removed
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17 |
;* In addition, the six registers forming the three data pointers X, Y and |
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include m168def.inc with #directives removed
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
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;* SRAM is also defined |
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;* |
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;* The Register names are represented by their hexadecimal address. |
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22 |
;* |
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;* The Register Bit names are represented by their bit number (0-7). |
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;* |
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;* Please observe the difference in using the bit names with instructions |
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
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;* (skip if bit in register set/cleared). The following example illustrates |
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;* this: |
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;* |
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;* in r16,PORTB ;read PORTB latch |
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
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;* out PORTB,r16 ;output to PORTB |
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;* |
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;* in r16,TIFR ;read the Timer Interrupt Flag Register |
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
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;* rjmp TOV0_is_set ;jump if set |
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;* ... ;otherwise do something else |
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;************************************************************************* |
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|
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; #ifndef _M168DEF_INC_ |
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; #define _M168DEF_INC_ |
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; #pragma partinc 0 |
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|
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; ***** SPECIFY DEVICE *************************************************** |
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include m168def.inc with #directives removed
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47 |
.device ATmega168 |
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; #pragma AVRPART ADMIN PART_NAME ATmega168 |
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.equ SIGNATURE_000 = 0x1e |
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.equ SIGNATURE_001 = 0x94 |
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.equ SIGNATURE_002 = 0x06 |
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|
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; #pragma AVRPART CORE CORE_VERSION V2E |
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|
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|
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; ***** I/O REGISTER DEFINITIONS ***************************************** |
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57 |
; NOTE: |
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; Definitions marked "MEMORY MAPPED"are extended I/O ports |
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; and cannot be used with IN/OUT instructions |
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60 |
.equ UDR0 = 0xc6 ; MEMORY MAPPED |
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61 |
.equ UBRR0H = 0xc5 ; MEMORY MAPPED |
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.equ UBRR0L = 0xc4 ; MEMORY MAPPED |
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63 |
.equ UCSR0C = 0xc2 ; MEMORY MAPPED |
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64 |
.equ UCSR0B = 0xc1 ; MEMORY MAPPED |
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65 |
.equ UCSR0A = 0xc0 ; MEMORY MAPPED |
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66 |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
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67 |
.equ TWCR = 0xbc ; MEMORY MAPPED |
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68 |
.equ TWDR = 0xbb ; MEMORY MAPPED |
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69 |
.equ TWAR = 0xba ; MEMORY MAPPED |
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70 |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
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71 |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
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72 |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
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73 |
.equ OCR2B = 0xb4 ; MEMORY MAPPED |
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74 |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
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75 |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
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76 |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
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77 |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
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78 |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
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79 |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
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80 |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
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81 |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
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82 |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
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83 |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
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84 |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
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85 |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
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86 |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
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87 |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
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88 |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
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89 |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
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90 |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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91 |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
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92 |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
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93 |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
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94 |
.equ ADCH = 0x79 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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95 |
.equ ADCL = 0x78 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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96 |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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97 |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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98 |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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99 |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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100 |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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101 |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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102 |
.equ EICRA = 0x69 ; MEMORY MAPPED |
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103 |
.equ PCICR = 0x68 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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104 |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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105 |
.equ PRR = 0x64 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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106 |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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107 |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
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include m168def.inc with #directives removed
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108 |
.equ SREG = 0x3f |
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include m168def.inc with #directives removed
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109 |
.equ SPH = 0x3e |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
110 |
.equ SPL = 0x3d |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
111 |
.equ SPMCSR = 0x37 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
112 |
.equ MCUCR = 0x35 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
113 |
.equ MCUSR = 0x34 |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
114 |
.equ SMCR = 0x33 |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
115 |
.equ ACSR = 0x30 |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
116 |
.equ SPDR = 0x2e |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
117 |
.equ SPSR = 0x2d |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
118 |
.equ SPCR = 0x2c |
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Tero Marttila <terom@fixme.fi>
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changeset
|
119 |
.equ GPIOR2 = 0x2b |
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Tero Marttila <terom@fixme.fi>
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|
120 |
.equ GPIOR1 = 0x2a |
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|
121 |
.equ OCR0B = 0x28 |
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|
122 |
.equ OCR0A = 0x27 |
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Tero Marttila <terom@fixme.fi>
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|
123 |
.equ TCNT0 = 0x26 |
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Tero Marttila <terom@fixme.fi>
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|
124 |
.equ TCCR0B = 0x25 |
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|
125 |
.equ TCCR0A = 0x24 |
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Tero Marttila <terom@fixme.fi>
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|
126 |
.equ GTCCR = 0x23 |
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Tero Marttila <terom@fixme.fi>
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|
127 |
.equ EEARH = 0x22 |
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Tero Marttila <terom@fixme.fi>
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|
128 |
.equ EEARL = 0x21 |
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Tero Marttila <terom@fixme.fi>
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|
129 |
.equ EEDR = 0x20 |
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Tero Marttila <terom@fixme.fi>
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|
130 |
.equ EECR = 0x1f |
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Tero Marttila <terom@fixme.fi>
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changeset
|
131 |
.equ GPIOR0 = 0x1e |
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Tero Marttila <terom@fixme.fi>
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|
132 |
.equ EIMSK = 0x1d |
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Tero Marttila <terom@fixme.fi>
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changeset
|
133 |
.equ EIFR = 0x1c |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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changeset
|
134 |
.equ PCIFR = 0x1b |
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Tero Marttila <terom@fixme.fi>
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diff
changeset
|
135 |
.equ TIFR2 = 0x17 |
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Tero Marttila <terom@fixme.fi>
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diff
changeset
|
136 |
.equ TIFR1 = 0x16 |
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Tero Marttila <terom@fixme.fi>
parents:
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|
137 |
.equ TIFR0 = 0x15 |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
138 |
.equ PORTD = 0x0b |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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changeset
|
139 |
.equ DDRD = 0x0a |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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changeset
|
140 |
.equ PIND = 0x09 |
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
141 |
.equ PORTC = 0x08 |
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Tero Marttila <terom@fixme.fi>
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changeset
|
142 |
.equ DDRC = 0x07 |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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diff
changeset
|
143 |
.equ PINC = 0x06 |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
144 |
.equ PORTB = 0x05 |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
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changeset
|
145 |
.equ DDRB = 0x04 |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
146 |
.equ PINB = 0x03 |
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changeset
|
147 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
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parents:
diff
changeset
|
148 |
|
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include m168def.inc with #directives removed
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changeset
|
149 |
; ***** BIT DEFINITIONS ************************************************** |
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changeset
|
150 |
|
e0b8d42c62e1
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Tero Marttila <terom@fixme.fi>
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diff
changeset
|
151 |
; ***** USART0 *********************** |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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changeset
|
152 |
; UDR0 - USART I/O Data Register |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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|
153 |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
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|
154 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
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|
155 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
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Tero Marttila <terom@fixme.fi>
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|
156 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
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Tero Marttila <terom@fixme.fi>
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|
157 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
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Tero Marttila <terom@fixme.fi>
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|
158 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
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Tero Marttila <terom@fixme.fi>
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changeset
|
159 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
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Tero Marttila <terom@fixme.fi>
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|
160 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
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changeset
|
161 |
|
e0b8d42c62e1
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
162 |
; UCSR0A - USART Control and Status Register A |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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diff
changeset
|
163 |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
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include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
164 |
.equ U2X0 = 1 ; Double the USART transmission speed |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
165 |
.equ UPE0 = 2 ; Parity Error |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
166 |
.equ DOR0 = 3 ; Data overRun |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
167 |
.equ FE0 = 4 ; Framing Error |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
168 |
.equ UDRE0 = 5 ; USART Data Register Empty |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
169 |
.equ TXC0 = 6 ; USART Transmitt Complete |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
170 |
.equ RXC0 = 7 ; USART Receive Complete |
e0b8d42c62e1
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Tero Marttila <terom@fixme.fi>
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diff
changeset
|
171 |
|
e0b8d42c62e1
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
172 |
; UCSR0B - USART Control and Status Register B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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diff
changeset
|
173 |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
174 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
175 |
.equ UCSZ02 = 2 ; Character Size |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
176 |
.equ TXEN0 = 3 ; Transmitter Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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diff
changeset
|
177 |
.equ RXEN0 = 4 ; Receiver Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
178 |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
179 |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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diff
changeset
|
180 |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
e0b8d42c62e1
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
181 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
182 |
; UCSR0C - USART Control and Status Register C |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
183 |
.equ UCPOL0 = 0 ; Clock Polarity |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
184 |
.equ UCSZ00 = 1 ; Character Size |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
185 |
.equ UCPHA0 = UCSZ00 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
186 |
.equ UCSZ01 = 2 ; Character Size |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
187 |
.equ UDORD0 = UCSZ01 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
188 |
.equ USBS0 = 3 ; Stop Bit Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
189 |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
190 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
191 |
.equ UMSEL00 = 6 ; USART Mode Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
192 |
.equ UMSEL0 = UMSEL00 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
193 |
.equ UMSEL01 = 7 ; USART Mode Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
194 |
.equ UMSEL1 = UMSEL01 ; For compatibility |
e0b8d42c62e1
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Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
195 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
196 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
197 |
; ***** TWI ************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
198 |
; TWAMR - TWI (Slave) Address Mask Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
199 |
.equ TWAM0 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
200 |
.equ TWAMR0 = TWAM0 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
201 |
.equ TWAM1 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
202 |
.equ TWAMR1 = TWAM1 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
203 |
.equ TWAM2 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
204 |
.equ TWAMR2 = TWAM2 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
205 |
.equ TWAM3 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
206 |
.equ TWAMR3 = TWAM3 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
207 |
.equ TWAM4 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
208 |
.equ TWAMR4 = TWAM4 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
209 |
.equ TWAM5 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
210 |
.equ TWAMR5 = TWAM5 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
211 |
.equ TWAM6 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
212 |
.equ TWAMR6 = TWAM6 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
213 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
214 |
; TWBR - TWI Bit Rate register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
215 |
.equ TWBR0 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
216 |
.equ TWBR1 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
217 |
.equ TWBR2 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
218 |
.equ TWBR3 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
219 |
.equ TWBR4 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
220 |
.equ TWBR5 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
221 |
.equ TWBR6 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
222 |
.equ TWBR7 = 7 ; |
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223 |
|
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224 |
; TWCR - TWI Control Register |
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225 |
.equ TWIE = 0 ; TWI Interrupt Enable |
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226 |
.equ TWEN = 2 ; TWI Enable Bit |
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227 |
.equ TWWC = 3 ; TWI Write Collition Flag |
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228 |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
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229 |
.equ TWSTA = 5 ; TWI Start Condition Bit |
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230 |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
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231 |
.equ TWINT = 7 ; TWI Interrupt Flag |
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|
232 |
|
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233 |
; TWSR - TWI Status Register |
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234 |
.equ TWPS0 = 0 ; TWI Prescaler |
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235 |
.equ TWPS1 = 1 ; TWI Prescaler |
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236 |
.equ TWS3 = 3 ; TWI Status |
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237 |
.equ TWS4 = 4 ; TWI Status |
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238 |
.equ TWS5 = 5 ; TWI Status |
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239 |
.equ TWS6 = 6 ; TWI Status |
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240 |
.equ TWS7 = 7 ; TWI Status |
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|
241 |
|
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242 |
; TWDR - TWI Data register |
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243 |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
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244 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
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245 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
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246 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
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247 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
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248 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
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249 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
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250 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
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|
251 |
|
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|
252 |
; TWAR - TWI (Slave) Address register |
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253 |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
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254 |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
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255 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
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256 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
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257 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
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258 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
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259 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
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260 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
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|
261 |
|
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|
262 |
|
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263 |
; ***** TIMER_COUNTER_1 ************** |
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|
264 |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
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265 |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
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|
266 |
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
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267 |
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
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268 |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
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|
269 |
|
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|
270 |
; TIFR1 - Timer/Counter Interrupt Flag register |
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271 |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
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272 |
.equ OCF1A = 1 ; Output Compare Flag 1A |
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273 |
.equ OCF1B = 2 ; Output Compare Flag 1B |
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274 |
.equ ICF1 = 5 ; Input Capture Flag 1 |
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275 |
|
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276 |
; TCCR1A - Timer/Counter1 Control Register A |
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277 |
.equ WGM10 = 0 ; Waveform Generation Mode |
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278 |
.equ WGM11 = 1 ; Waveform Generation Mode |
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279 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
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280 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
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281 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
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282 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
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|
283 |
|
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|
284 |
; TCCR1B - Timer/Counter1 Control Register B |
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|
285 |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
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|
286 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
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|
287 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
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|
288 |
.equ WGM12 = 3 ; Waveform Generation Mode |
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|
289 |
.equ WGM13 = 4 ; Waveform Generation Mode |
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|
290 |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
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|
291 |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
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changeset
|
292 |
|
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|
293 |
; TCCR1C - Timer/Counter1 Control Register C |
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|
294 |
.equ FOC1B = 6 ; |
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|
295 |
.equ FOC1A = 7 ; |
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changeset
|
296 |
|
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|
297 |
; GTCCR - General Timer/Counter Control Register |
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|
298 |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
e0b8d42c62e1
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|
299 |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
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changeset
|
300 |
|
e0b8d42c62e1
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changeset
|
301 |
|
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|
302 |
; ***** TIMER_COUNTER_2 ************** |
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include m168def.inc with #directives removed
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changeset
|
303 |
; TIMSK2 - Timer/Counter Interrupt Mask register |
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include m168def.inc with #directives removed
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|
304 |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
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changeset
|
305 |
.equ TOIE2A = TOIE2 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
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|
306 |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable |
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|
307 |
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable |
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changeset
|
308 |
|
e0b8d42c62e1
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changeset
|
309 |
; TIFR2 - Timer/Counter Interrupt Flag Register |
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include m168def.inc with #directives removed
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changeset
|
310 |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
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include m168def.inc with #directives removed
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|
311 |
.equ OCF2A = 1 ; Output Compare Flag 2A |
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|
312 |
.equ OCF2B = 2 ; Output Compare Flag 2B |
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changeset
|
313 |
|
e0b8d42c62e1
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changeset
|
314 |
; TCCR2A - Timer/Counter2 Control Register A |
e0b8d42c62e1
include m168def.inc with #directives removed
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changeset
|
315 |
.equ WGM20 = 0 ; Waveform Genration Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
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|
316 |
.equ WGM21 = 1 ; Waveform Genration Mode |
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|
317 |
.equ COM2B0 = 4 ; Compare Output Mode bit 0 |
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|
318 |
.equ COM2B1 = 5 ; Compare Output Mode bit 1 |
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|
319 |
.equ COM2A0 = 6 ; Compare Output Mode bit 1 |
e0b8d42c62e1
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|
320 |
.equ COM2A1 = 7 ; Compare Output Mode bit 1 |
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changeset
|
321 |
|
e0b8d42c62e1
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diff
changeset
|
322 |
; TCCR2B - Timer/Counter2 Control Register B |
e0b8d42c62e1
include m168def.inc with #directives removed
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changeset
|
323 |
.equ CS20 = 0 ; Clock Select bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
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changeset
|
324 |
.equ CS21 = 1 ; Clock Select bit 1 |
e0b8d42c62e1
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|
325 |
.equ CS22 = 2 ; Clock Select bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
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|
326 |
.equ WGM22 = 3 ; Waveform Generation Mode |
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include m168def.inc with #directives removed
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changeset
|
327 |
.equ FOC2B = 6 ; Force Output Compare B |
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include m168def.inc with #directives removed
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|
328 |
.equ FOC2A = 7 ; Force Output Compare A |
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changeset
|
329 |
|
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changeset
|
330 |
; TCNT2 - Timer/Counter2 |
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include m168def.inc with #directives removed
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changeset
|
331 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
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include m168def.inc with #directives removed
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changeset
|
332 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
333 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
334 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
335 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
336 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
337 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
338 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
339 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
340 |
; OCR2A - Timer/Counter2 Output Compare Register A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
341 |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
342 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
343 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
344 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
345 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
346 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
347 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
348 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
349 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
350 |
; OCR2B - Timer/Counter2 Output Compare Register B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
351 |
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
352 |
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
353 |
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
354 |
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
355 |
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
356 |
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
357 |
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
358 |
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
359 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
360 |
; ASSR - Asynchronous Status Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
361 |
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
362 |
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
363 |
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
364 |
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
365 |
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
366 |
.equ AS2 = 5 ; Asynchronous Timer/Counter2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
367 |
.equ EXCLK = 6 ; Enable External Clock Input |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
368 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
369 |
; GTCCR - General Timer Counter Control register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
370 |
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
371 |
.equ PSR2 = PSRASY ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
372 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
373 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
374 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
375 |
; ***** AD_CONVERTER ***************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
376 |
; ADMUX - The ADC multiplexer Selection Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
377 |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
378 |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
379 |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
380 |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
381 |
.equ ADLAR = 5 ; Left Adjust Result |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
382 |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
383 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
384 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
385 |
; ADCSRA - The ADC Control and Status register A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
386 |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
387 |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
388 |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
389 |
.equ ADIE = 3 ; ADC Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
390 |
.equ ADIF = 4 ; ADC Interrupt Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
391 |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
392 |
.equ ADSC = 6 ; ADC Start Conversion |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
393 |
.equ ADEN = 7 ; ADC Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
394 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
395 |
; ADCSRB - The ADC Control and Status register B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
396 |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
397 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
398 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
399 |
.equ ACME = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
400 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
401 |
; ADCH - ADC Data Register High Byte |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
402 |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
403 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
404 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
405 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
406 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
407 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
408 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
409 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
410 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
411 |
; ADCL - ADC Data Register Low Byte |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
412 |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
413 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
414 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
415 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
416 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
417 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
418 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
419 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
420 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
421 |
; DIDR0 - Digital Input Disable Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
422 |
.equ ADC0D = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
423 |
.equ ADC1D = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
424 |
.equ ADC2D = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
425 |
.equ ADC3D = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
426 |
.equ ADC4D = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
427 |
.equ ADC5D = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
428 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
429 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
430 |
; ***** ANALOG_COMPARATOR ************ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
431 |
; ACSR - Analog Comparator Control And Status Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
432 |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
433 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
434 |
.equ ACIC = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
435 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
436 |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
437 |
.equ ACO = 5 ; Analog Compare Output |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
438 |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
439 |
.equ ACD = 7 ; Analog Comparator Disable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
440 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
441 |
; DIDR1 - Digital Input Disable Register 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
442 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
443 |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
444 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
445 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
446 |
; ***** PORTB ************************ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
447 |
; PORTB - Port B Data Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
448 |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
449 |
.equ PB0 = 0 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
450 |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
451 |
.equ PB1 = 1 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
452 |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
453 |
.equ PB2 = 2 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
454 |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
455 |
.equ PB3 = 3 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
456 |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
457 |
.equ PB4 = 4 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
458 |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
459 |
.equ PB5 = 5 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
460 |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
461 |
.equ PB6 = 6 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
462 |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
463 |
.equ PB7 = 7 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
464 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
465 |
; DDRB - Port B Data Direction Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
466 |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
467 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
468 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
469 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
470 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
471 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
472 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
473 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
474 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
475 |
; PINB - Port B Input Pins |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
476 |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
477 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
478 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
479 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
480 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
481 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
482 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
483 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
484 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
485 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
486 |
; ***** PORTC ************************ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
487 |
; PORTC - Port C Data Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
488 |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
489 |
.equ PC0 = 0 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
490 |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
491 |
.equ PC1 = 1 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
492 |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
493 |
.equ PC2 = 2 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
494 |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
495 |
.equ PC3 = 3 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
496 |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
497 |
.equ PC4 = 4 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
498 |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
499 |
.equ PC5 = 5 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
500 |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
501 |
.equ PC6 = 6 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
502 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
503 |
; DDRC - Port C Data Direction Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
504 |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
505 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
506 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
507 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
508 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
509 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
510 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
511 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
512 |
; PINC - Port C Input Pins |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
513 |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
514 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
515 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
516 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
517 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
518 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
519 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
520 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
521 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
522 |
; ***** PORTD ************************ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
523 |
; PORTD - Port D Data Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
524 |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
525 |
.equ PD0 = 0 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
526 |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
527 |
.equ PD1 = 1 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
528 |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
529 |
.equ PD2 = 2 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
530 |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
531 |
.equ PD3 = 3 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
532 |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
533 |
.equ PD4 = 4 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
534 |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
535 |
.equ PD5 = 5 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
536 |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
537 |
.equ PD6 = 6 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
538 |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
539 |
.equ PD7 = 7 ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
540 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
541 |
; DDRD - Port D Data Direction Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
542 |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
543 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
544 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
545 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
546 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
547 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
548 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
549 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
550 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
551 |
; PIND - Port D Input Pins |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
552 |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
553 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
554 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
555 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
556 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
557 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
558 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
559 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
560 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
561 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
562 |
; ***** TIMER_COUNTER_0 ************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
563 |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
564 |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
565 |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
566 |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
567 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
568 |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
569 |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
570 |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
571 |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
572 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
573 |
; TCCR0A - Timer/Counter Control Register A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
574 |
.equ WGM00 = 0 ; Waveform Generation Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
575 |
.equ WGM01 = 1 ; Waveform Generation Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
576 |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
577 |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
578 |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
579 |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
580 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
581 |
; TCCR0B - Timer/Counter Control Register B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
582 |
.equ CS00 = 0 ; Clock Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
583 |
.equ CS01 = 1 ; Clock Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
584 |
.equ CS02 = 2 ; Clock Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
585 |
.equ WGM02 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
586 |
.equ FOC0B = 6 ; Force Output Compare B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
587 |
.equ FOC0A = 7 ; Force Output Compare A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
588 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
589 |
; TCNT0 - Timer/Counter0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
590 |
.equ TCNT0_0 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
591 |
.equ TCNT0_1 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
592 |
.equ TCNT0_2 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
593 |
.equ TCNT0_3 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
594 |
.equ TCNT0_4 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
595 |
.equ TCNT0_5 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
596 |
.equ TCNT0_6 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
597 |
.equ TCNT0_7 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
598 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
599 |
; OCR0A - Timer/Counter0 Output Compare Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
600 |
.equ OCROA_0 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
601 |
.equ OCROA_1 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
602 |
.equ OCROA_2 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
603 |
.equ OCROA_3 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
604 |
.equ OCROA_4 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
605 |
.equ OCROA_5 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
606 |
.equ OCROA_6 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
607 |
.equ OCROA_7 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
608 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
609 |
; OCR0B - Timer/Counter0 Output Compare Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
610 |
.equ OCR0B_0 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
611 |
.equ OCR0B_1 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
612 |
.equ OCR0B_2 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
613 |
.equ OCR0B_3 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
614 |
.equ OCR0B_4 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
615 |
.equ OCR0B_5 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
616 |
.equ OCR0B_6 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
617 |
.equ OCR0B_7 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
618 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
619 |
; GTCCR - General Timer/Counter Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
620 |
;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
621 |
.equ PSR10 = PSRSYNC ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
622 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
623 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
624 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
625 |
; ***** EXTERNAL_INTERRUPT *********** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
626 |
; EICRA - External Interrupt Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
627 |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
628 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
629 |
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
630 |
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
631 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
632 |
; EIMSK - External Interrupt Mask Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
633 |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
634 |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
635 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
636 |
; EIFR - External Interrupt Flag Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
637 |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
638 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
639 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
640 |
; PCMSK2 - Pin Change Mask Register 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
641 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
642 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
643 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
644 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
645 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
646 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
647 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
648 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
649 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
650 |
; PCMSK1 - Pin Change Mask Register 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
651 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
652 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
653 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
654 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
655 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
656 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
657 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
658 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
659 |
; PCMSK0 - Pin Change Mask Register 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
660 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
661 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
662 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
663 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
664 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
665 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
666 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
667 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
668 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
669 |
; PCIFR - Pin Change Interrupt Flag Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
670 |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
671 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
672 |
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
673 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
674 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
675 |
; ***** SPI ************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
676 |
; SPDR - SPI Data Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
677 |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
678 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
679 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
680 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
681 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
682 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
683 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
684 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
685 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
686 |
; SPSR - SPI Status Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
687 |
.equ SPI2X = 0 ; Double SPI Speed Bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
688 |
.equ WCOL = 6 ; Write Collision Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
689 |
.equ SPIF = 7 ; SPI Interrupt Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
690 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
691 |
; SPCR - SPI Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
692 |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
693 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
694 |
.equ CPHA = 2 ; Clock Phase |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
695 |
.equ CPOL = 3 ; Clock polarity |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
696 |
.equ MSTR = 4 ; Master/Slave Select |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
697 |
.equ DORD = 5 ; Data Order |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
698 |
.equ SPE = 6 ; SPI Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
699 |
.equ SPIE = 7 ; SPI Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
700 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
701 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
702 |
; ***** CPU ************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
703 |
; SREG - Status Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
704 |
.equ SREG_C = 0 ; Carry Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
705 |
.equ SREG_Z = 1 ; Zero Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
706 |
.equ SREG_N = 2 ; Negative Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
707 |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
708 |
.equ SREG_S = 4 ; Sign Bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
709 |
.equ SREG_H = 5 ; Half Carry Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
710 |
.equ SREG_T = 6 ; Bit Copy Storage |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
711 |
.equ SREG_I = 7 ; Global Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
712 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
713 |
; OSCCAL - Oscillator Calibration Value |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
714 |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
715 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
716 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
717 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
718 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
719 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
720 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
721 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
722 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
723 |
; CLKPR - Clock Prescale Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
724 |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
725 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
726 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
727 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
728 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
729 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
730 |
; SPMCSR - Store Program Memory Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
731 |
.equ SELFPRGEN = 0 ; Self Programming Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
732 |
.equ PGERS = 1 ; Page Erase |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
733 |
.equ PGWRT = 2 ; Page Write |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
734 |
.equ BLBSET = 3 ; Boot Lock Bit Set |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
735 |
.equ RWWSRE = 4 ; Read-While-Write section read enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
736 |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
737 |
.equ SPMIE = 7 ; SPM Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
738 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
739 |
; MCUCR - MCU Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
740 |
.equ IVCE = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
741 |
.equ IVSEL = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
742 |
.equ PUD = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
743 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
744 |
; MCUSR - MCU Status Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
745 |
.equ PORF = 0 ; Power-on reset flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
746 |
.equ EXTRF = 1 ; External Reset Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
747 |
.equ EXTREF = EXTRF ; For compatibility |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
748 |
.equ BORF = 2 ; Brown-out Reset Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
749 |
.equ WDRF = 3 ; Watchdog Reset Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
750 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
751 |
; SMCR - |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
752 |
.equ SE = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
753 |
.equ SM0 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
754 |
.equ SM1 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
755 |
.equ SM2 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
756 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
757 |
; GPIOR2 - General Purpose I/O Register 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
758 |
.equ GPIOR20 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
759 |
.equ GPIOR21 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
760 |
.equ GPIOR22 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
761 |
.equ GPIOR23 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
762 |
.equ GPIOR24 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
763 |
.equ GPIOR25 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
764 |
.equ GPIOR26 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
765 |
.equ GPIOR27 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
766 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
767 |
; GPIOR1 - General Purpose I/O Register 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
768 |
.equ GPIOR10 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
769 |
.equ GPIOR11 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
770 |
.equ GPIOR12 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
771 |
.equ GPIOR13 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
772 |
.equ GPIOR14 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
773 |
.equ GPIOR15 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
774 |
.equ GPIOR16 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
775 |
.equ GPIOR17 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
776 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
777 |
; GPIOR0 - General Purpose I/O Register 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
778 |
.equ GPIOR00 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
779 |
.equ GPIOR01 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
780 |
.equ GPIOR02 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
781 |
.equ GPIOR03 = 3 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
782 |
.equ GPIOR04 = 4 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
783 |
.equ GPIOR05 = 5 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
784 |
.equ GPIOR06 = 6 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
785 |
.equ GPIOR07 = 7 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
786 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
787 |
; PRR - Power Reduction Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
788 |
.equ PRADC = 0 ; Power Reduction ADC |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
789 |
.equ PRUSART0 = 1 ; Power Reduction USART |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
790 |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
791 |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
792 |
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
793 |
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
794 |
.equ PRTWI = 7 ; Power Reduction TWI |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
795 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
796 |
; PCICR - |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
797 |
.equ PCIE0 = 0 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
798 |
.equ PCIE1 = 1 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
799 |
.equ PCIE2 = 2 ; |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
800 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
801 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
802 |
; ***** WATCHDOG ********************* |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
803 |
; WDTCSR - Watchdog Timer Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
804 |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
805 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
806 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
807 |
.equ WDE = 3 ; Watch Dog Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
808 |
.equ WDCE = 4 ; Watchdog Change Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
809 |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
810 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
811 |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
812 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
813 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
814 |
; ***** EEPROM *********************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
815 |
; EEARL - EEPROM Address Register Low Byte |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
816 |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
817 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
818 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
819 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
820 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
821 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
822 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
823 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
824 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
825 |
; EEARH - EEPROM Address Register High Byte |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
826 |
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
827 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
828 |
; EEDR - EEPROM Data Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
829 |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
830 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
831 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
832 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
833 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
834 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
835 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
836 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
837 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
838 |
; EECR - EEPROM Control Register |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
839 |
.equ EERE = 0 ; EEPROM Read Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
840 |
.equ EEPE = 1 ; EEPROM Write Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
841 |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
842 |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
843 |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
844 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
845 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
846 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
847 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
848 |
; ***** LOCKSBITS ******************************************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
849 |
.equ LB1 = 0 ; Lock bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
850 |
.equ LB2 = 1 ; Lock bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
851 |
.equ BLB01 = 2 ; Boot Lock bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
852 |
.equ BLB02 = 3 ; Boot Lock bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
853 |
.equ BLB11 = 4 ; Boot lock bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
854 |
.equ BLB12 = 5 ; Boot lock bit |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
855 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
856 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
857 |
; ***** FUSES ************************************************************ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
858 |
; LOW fuse bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
859 |
.equ CKSEL0 = 0 ; Select Clock Source |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
860 |
.equ CKSEL1 = 1 ; Select Clock Source |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
861 |
.equ CKSEL2 = 2 ; Select Clock Source |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
862 |
.equ CKSEL3 = 3 ; Select Clock Source |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
863 |
.equ SUT0 = 4 ; Select start-up time |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
864 |
.equ SUT1 = 5 ; Select start-up time |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
865 |
.equ CKOUT = 6 ; Clock output |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
866 |
.equ CKDIV8 = 7 ; Divide clock by 8 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
867 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
868 |
; HIGH fuse bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
869 |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
870 |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
871 |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
872 |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
873 |
.equ WDTON = 4 ; Watchdog Timer Always On |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
874 |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
875 |
.equ DWEN = 6 ; debugWIRE Enable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
876 |
.equ RSTDISBL = 7 ; External reset disable |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
877 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
878 |
; EXTENDED fuse bits |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
879 |
.equ BOOTRST = 0 ; Select reset vector |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
880 |
.equ BOOTSZ0 = 1 ; Select boot size |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
881 |
.equ BOOTSZ1 = 2 ; Select boot size |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
882 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
883 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
884 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
885 |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
886 |
.def XH = r27 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
887 |
.def XL = r26 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
888 |
.def YH = r29 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
889 |
.def YL = r28 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
890 |
.def ZH = r31 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
891 |
.def ZL = r30 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
892 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
893 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
894 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
895 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
896 |
.equ FLASHEND = 0x1fff ; Note: Word address |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
897 |
.equ IOEND = 0x00ff |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
898 |
.equ SRAM_START = 0x0100 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
899 |
.equ SRAM_SIZE = 1024 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
900 |
.equ RAMEND = 0x04ff |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
901 |
.equ XRAMEND = 0x0000 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
902 |
.equ E2END = 0x01ff |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
903 |
.equ EEPROMEND = 0x01ff |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
904 |
.equ EEADRBITS = 9 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
905 |
; #pragma AVRPART MEMORY PROG_FLASH 16384 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
906 |
; #pragma AVRPART MEMORY EEPROM 512 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
907 |
; #pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
908 |
; #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
909 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
910 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
911 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
912 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
913 |
.equ NRWW_START_ADDR = 0x1c00 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
914 |
.equ NRWW_STOP_ADDR = 0x1fff |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
915 |
.equ RWW_START_ADDR = 0x0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
916 |
.equ RWW_STOP_ADDR = 0x1bff |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
917 |
.equ PAGESIZE = 64 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
918 |
.equ FIRSTBOOTSTART = 0x1f80 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
919 |
.equ SECONDBOOTSTART = 0x1f00 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
920 |
.equ THIRDBOOTSTART = 0x1e00 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
921 |
.equ FOURTHBOOTSTART = 0x1c00 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
922 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
923 |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
924 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
925 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
926 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
927 |
; ***** INTERRUPT VECTORS ************************************************ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
928 |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
929 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
930 |
.equ PCI0addr = 0x0006 ; Pin Change Interrupt Request 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
931 |
.equ PCI1addr = 0x0008 ; Pin Change Interrupt Request 0 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
932 |
.equ PCI2addr = 0x000a ; Pin Change Interrupt Request 1 |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
933 |
.equ WDTaddr = 0x000c ; Watchdog Time-out Interrupt |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
934 |
.equ OC2Aaddr = 0x000e ; Timer/Counter2 Compare Match A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
935 |
.equ OC2Baddr = 0x0010 ; Timer/Counter2 Compare Match A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
936 |
.equ OVF2addr = 0x0012 ; Timer/Counter2 Overflow |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
937 |
.equ ICP1addr = 0x0014 ; Timer/Counter1 Capture Event |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
938 |
.equ OC1Aaddr = 0x0016 ; Timer/Counter1 Compare Match A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
939 |
.equ OC1Baddr = 0x0018 ; Timer/Counter1 Compare Match B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
940 |
.equ OVF1addr = 0x001a ; Timer/Counter1 Overflow |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
941 |
.equ OC0Aaddr = 0x001c ; TimerCounter0 Compare Match A |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
942 |
.equ OC0Baddr = 0x001e ; TimerCounter0 Compare Match B |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
943 |
.equ OVF0addr = 0x0020 ; Timer/Couner0 Overflow |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
944 |
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
945 |
.equ URXCaddr = 0x0024 ; USART Rx Complete |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
946 |
.equ UDREaddr = 0x0026 ; USART, Data Register Empty |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
947 |
.equ UTXCaddr = 0x0028 ; USART Tx Complete |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
948 |
.equ ADCCaddr = 0x002a ; ADC Conversion Complete |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
949 |
.equ ERDYaddr = 0x002c ; EEPROM Ready |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
950 |
.equ ACIaddr = 0x002e ; Analog Comparator |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
951 |
.equ TWIaddr = 0x0030 ; Two-wire Serial Interface |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
952 |
.equ SPMRaddr = 0x0032 ; Store Program Memory Read |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
953 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
954 |
.equ INT_VECTORS_SIZE = 52 ; size in words |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
955 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
956 |
; #endif /* _M168DEF_INC_ */ |
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
957 |
|
e0b8d42c62e1
include m168def.inc with #directives removed
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
958 |
; ***** END OF FILE ****************************************************** |