qmsk-dmx: timer.inc@ec6271f0637b (annotated)

18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	1	;; vim: filetype=avr
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	2	;;
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	3	;; Timer unit control and use
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	4	;;
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	5
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	6	.equ TIMER_FLAGS = GPIOR0
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	7
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	8	;; Timer0
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	9	; Compare output mode
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	10	.set TIMER0_COMA = 0b00 ; null
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	11	.set TIMER0_COMB = 0b00 ; null
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	12
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	13	; Waveform Generation Mode (triplet low/high)
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	14	.set TIMER0_WGML = 0b10 ; CTC
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	15	.set TIMER0_WGMH = 0b0 ; CTC
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	16
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	17	; Clock Source
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	18	.set TIMER0_CS = 0b101 ; 1/1024
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	19
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	20	;; Timer1
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	21	; Waveform Generation Mode (nibble low/high)
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	22	.set TIMER1_WGML = 0b00 ; CTC
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	23	.set TIMER1_WGMH = 0b01 ; CTC
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	24
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	25	; Clock Source
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	26	.set TIMER1_CS = 0b101 ; 1/1024
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	27
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	28	; Flags
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	29	.equ TIMER1_BUSY = 1
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	30
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	31	.set SLEEP_MODE = 0b000 ; Idle
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	32
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	33	Timer_Init:
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	34	Timer0_Init:
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	35	; OC0A/B disconnected from output
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	36	; No PWM mode
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	37	ldi r16, (TIMER0_COMA << COM0A0) \| (TIMER0_COMB << COM0B0) \| (TIMER0_WGML << WGM00)
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	38	out TCCR0A, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	39
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	40	; Clear
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	41	ldi r16, 0
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	42	out OCR0A, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	43	out OCR0B, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	44	out TCCR0B, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	45
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	46	; Enable compare interrupt
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	47	ldi r16, (1 << OCIE0A)
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	48	sts TIMSK0, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	49
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	50	Timer1_Init:
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	51	; OC1A/B disconnected from output
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	52	; No PWM mode
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	53	poke [TCCR1A, r16, (0b00 << COM1A0) \| (0b00 << COM1B0) \| (TIMER1_WGML << WGM10)]
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	54
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	55	; Clear
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	56	poke [TCCR1B, r16, 0]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	57	poke [TCCR1C, r16, 0]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	58
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	59	; Enable compare interrupt
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	60	poke [TIMSK1, r16, (1 << OCIE1A)]
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	61
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	62	Sleep_init:
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	63	; Select sleep mode
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	64	; Enable `sleep`
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	65	poke [SMCR, r16, (SLEEP_MODE << SM0) \| (1 << SE)]
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	66
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	67	; Disable ADC
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	68	poke [SMCR, r16, (1 << PRTWI) \| (1 << PRUSART0) \| (1 << PRADC)]
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	69
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	70	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	71
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	72	;; Timer0 is recurring; this starts it running, and it keeps hitting OC0A periodically
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	73	;; Input: r16 (period, in 1k-cycles)
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	74	Timer0_Start:
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	75	; Initialize timer
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	76	; set CTC trigger from r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	77	out OCR0A, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	78
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	79	; clear counter
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	80	ldi r16, 0
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	81	out TCNT0, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	82
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	83	; Start
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	84	; WGM
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	85	; Clock Source
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	86	ldi r16, (TIMER0_WGMH << WGM02) \| (TIMER0_CS << CS00)
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	87	out TCCR0B, r16
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	88
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	89	ret
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	90
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	91	Timer0_Read8:
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	92	in r16, TCNT0
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	93
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	94	ret
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	95
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	96	;; Timer0 Compare A interrupt handler
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	97	Timer_OC0A:
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	98	in r0, SREG
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	99
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	100	; Run callback
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	101	rcall TIMER0_CB_A
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	102
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	103	out SREG, r0
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	104	reti
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	105
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	106	;; Timer1 is one-shot; this starts it running, and it is then stopped once it hits OC1A
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	107	Timer1_Start:
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	108	; Initialize timer
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	109	poke [TCNT1H, r16, high(0)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	110	poke [TCNT1L, r16, low(0)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	111
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	112	; Set flag
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	113	sbi TIMER_FLAGS, TIMER1_BUSY
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	114
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	115	; Start
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	116	; WGM
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	117	; Clock Source
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	118	poke [TCCR1B, r16, (TIMER1_WGMH << WGM12) \| (TIMER1_CS << CS10)]
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	119
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	120	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	121
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	122	Timer1_Stop:
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	123	; WGM
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	124	; Clock off
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	125	poke [TCCR1B, r16, (TIMER1_WGMH << WGM12) \| (0b00 << CS10)]
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	126
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	127	; Clear flag
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	128	cbi TIMER_FLAGS, TIMER1_BUSY
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	129
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	130	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	131
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	132	;; Timer1 Compare A interrupt handler
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	133	Timer_OC1A:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	134	in r0, SREG
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	135
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	136	; Stop timer
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	137	rcall Timer1_Stop
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	138
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	139	out SREG, r0
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	140	reti
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	141
32 7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	142	;; Prime the timer and sleep for 1s
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	143	Timer_Sleep_1s:
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	144	; Initialize counter to 16k cycles
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	145	ldi XH, high(16 * 1024)
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	146	ldi XL, low(16 * 1024)
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	147
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	148	;; Continue
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	149
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	150	;; Count to X
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	151	Timer_Sleep:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	152	; Set TOP
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	153	sts OCR1AH, XH
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	154	sts OCR1AL, XL
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	155
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	156	; Start timer
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	157	rcall Timer1_Start
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	158
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	159	; Wait for timer to complete
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	160	_timer1_sleep:
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	161	sleep
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	162
29 453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	163	sbic TIMER_FLAGS, TIMER1_BUSY
453550e69e07 Test use of Timer0 Tero Marttila <terom@fixme.fi> parents: 21 diff changeset	164	rjmp _timer1_sleep
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	165
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	166	; Done
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	167	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	168
32 7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	169	;; Update timer for given timeout
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	170	Timer_Update:
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	171	; Set TOP
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	172	sts OCR1AH, XH
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	173	sts OCR1AL, XL
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	174
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	175	; Check timer
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	176	lds YL, TCNT1L
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	177	lds YH, TCNT1H
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	178
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	179	cp YL, XL
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	180	cpc YH, XH
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	181
32 7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	182	brlo timer_up_out
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	183
32 7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	184	; Update
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	185	; XXX: figure out a better way to do this...
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	186	ldi r16, 0
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	187	subi XL, 2
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	188	sbc XH, r16
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	189
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	190	sts TCNT1L, XL
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	191	sts TCNT1H, XH
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	192
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	193	timer_up_out:
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	194	; Done
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	195	ret
7ceb76b5a104 semi-broken Timer_Update mechanism Tero Marttila <terom@fixme.fi> parents: 29 diff changeset	196

author	Tero Marttila <terom@paivola.fi>
	Thu, 03 Apr 2014 19:44:13 +0300
changeset 51	ec6271f0637b
parent 32	7ceb76b5a104
permissions	-rw-r--r--