1 ;*************************************************************************** |
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2 ;* |
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3 ;* "div8u" - 8/8 Bit Unsigned Division |
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4 ;* |
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5 ;* This subroutine divides the two register variables "dd8u" (dividend) and |
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6 ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in |
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7 ;* "drem8u". |
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8 ;* |
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9 ;* Number of words :14 |
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10 ;* Number of cycles :97 |
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11 ;* Low registers used :1 (drem8u) |
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12 ;* High registers used :3 (dres8u/dd8u,dv8u,dcnt8u) |
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13 ;* |
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14 ;*************************************************************************** |
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15 |
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16 ;***** Subroutine Register Variables |
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17 |
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18 .def drem8u =r15 ;remainder |
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19 .def dres8u =r16 ;result |
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20 .def dd8u =r16 ;dividend |
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21 .def dv8u =r17 ;divisor |
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22 .def dcnt8u =r18 ;loop counter |
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23 |
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24 ;***** Code |
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25 |
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26 div8u: sub drem8u,drem8u ;clear remainder and carry |
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27 ldi dcnt8u,9 ;init loop counter |
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28 d8u_1: rol dd8u ;shift left dividend |
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29 dec dcnt8u ;decrement counter |
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30 brne d8u_2 ;if done |
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31 ret ; return |
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32 d8u_2: rol drem8u ;shift dividend into remainder |
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33 sub drem8u,dv8u ;remainder = remainder - divisor |
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34 brcc d8u_3 ;if result negative |
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35 add drem8u,dv8u ; restore remainder |
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36 clc ; clear carry to be shifted into result |
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37 rjmp d8u_1 ;else |
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38 d8u_3: sec ; set carry to be shifted into result |
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39 rjmp d8u_1 |
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40 |
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41 |
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