1 ;;; vim: set ft=avr: |
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2 |
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3 .nolist |
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4 .include "m168def.inc" ; Same family as 328P |
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5 .list |
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6 |
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7 .include "macros.inc" |
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8 |
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9 ;; Interrupt Vector |
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10 .cseg |
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11 .org 0x0000 |
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12 rjmp Main |
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13 |
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14 |
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15 ;; CPU cycles / second: 16 Mhz |
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16 .set CPU_CYCLES = 16 * 1000 * 1000 |
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17 |
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18 ;; Delays |
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19 .include "delay.inc" |
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20 |
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21 ;; DMX baud raite: 250k |
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22 .set DMX_BAUD = 250 * 1000 |
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23 |
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24 ;; CPU cycles / bit: 64 |
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25 .set DMX_CYCLES = CPU_CYCLES / DMX_BAUD |
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26 |
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27 ;; DMX output I/O |
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28 .set DMX_DDR = DDRB |
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29 .set DMX_PORT = PORTB |
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30 .equ DMX_DATA = PORTB3 |
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31 |
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32 ;; DMX protocol timer |
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33 ; Registers |
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34 .set DMX_TIMER_CRA = TCCR2A |
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35 .set DMX_TIMER_CRB = TCCR2B |
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36 .set DMX_TIMER_CNT = TCNT2 |
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37 .set DMX_TIMER_OCRA = OCR2A |
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38 .set DMX_TIMER_OCRB = OCR2B |
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39 .set DMX_TIMER_IMSK = TIMSK2 |
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40 .set DMX_TIMER_IFR = TIFR2 |
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41 |
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42 ; Compare output match isn't used |
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43 .set DMX_TIMER_COMA = 0b00 |
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44 .set DMX_TIMER_COMB = 0b00 |
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45 |
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46 ; Control register, generation mode value |
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47 .set DMX_TIMER_WGM_10 = 0b10 ; CTC |
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48 .set DMX_TIMER_WGM_2 = 0b0 |
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49 |
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50 ; Clock select |
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51 .set DMX_TIMER_CS_STOP = 0b000 |
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52 .set DMX_TIMER_CS = 0b001 ; 1/1 |
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53 ;.set DMX_TIMER_CS = 0b111 ; 1/1024 |
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54 |
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55 ; Counted value |
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56 .set DMX_TIMER_TOP = DMX_CYCLES ; number of cycles for baud |
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57 |
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58 ;; Debug LED |
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59 .set LED_DDR = DDRB |
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60 .set LED_PORT = PORTB |
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61 .set LED_PIN = PINB |
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62 .set LED_BIT = PORTB0 |
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63 |
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64 ;; Set up DMX output |
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65 DMX_Init: |
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66 ; Setup output port |
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67 ; out |
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68 sbi DMX_DDR, DMX_DATA |
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69 |
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70 ; drive high |
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71 sbi DMX_PORT, DMX_DATA |
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72 |
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73 ; Setup timer |
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74 ; setup CTC mode with no output pins |
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75 poke [DMX_TIMER_CRA, r16, (DMX_TIMER_COMA << COM2A0) | (DMX_TIMER_COMB << COM2B0) | (DMX_TIMER_WGM_10 << WGM20)] |
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76 poke [DMX_TIMER_CRB, r16, (DMX_TIMER_WGM_2 << WGM22) | (DMX_TIMER_CS_STOP << CS20)] |
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77 |
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78 ; trigger threshold for CTC |
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79 poke [DMX_TIMER_OCRA, r16, (DMX_TIMER_TOP)] |
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80 |
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81 ; OK |
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82 ret |
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83 |
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84 ;; Start Break signal |
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85 ;; |
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86 ;; 22 bits - 1s long; then DMX_Break_Mark |
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87 ;; |
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88 DMX_Break_Start: |
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89 ; Low |
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90 cbi DMX_PORT, DMX_DATA |
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91 |
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92 ret |
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93 |
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94 ;; Start Mark-after-break signal |
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95 ;; |
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96 ;; 2 bits - 1s long; then DMX_Break_End |
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97 ;; |
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98 DMX_Break_Mark: |
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99 ; High |
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100 sbi DMX_PORT, DMX_DATA |
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101 |
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102 ret |
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103 |
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104 ;; End break; prepare for DMX_Frame |
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105 DMX_Frame_Start: |
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106 ; Start timer |
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107 poke [DMX_TIMER_CRB, r20, (DMX_TIMER_WGM_2 << WGM22) | (DMX_TIMER_CS << CS20)] |
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108 |
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109 ret |
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110 |
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111 ;; Do a full DMX break, using some random length |
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112 ;; |
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113 DMX_Break: |
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114 ; Break |
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115 ; start |
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116 rcall DMX_Break_Start |
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117 |
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118 ; wait; about 100ms? |
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119 ldi r20, 82 / 10 |
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120 rcall VarDelay |
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121 |
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122 ; MAB |
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123 ; mark |
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124 rcall DMX_Break_Mark |
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125 |
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126 ; short wait |
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127 ldi r20, 1 |
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128 rcall VarDelay |
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129 |
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130 ; Timed frames |
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131 ; start frame |
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132 rcall DMX_Frame_Start |
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133 |
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134 ; ok |
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135 ret |
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136 |
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137 ;; Bitbang one DMX bit out |
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138 ;; uses SREG/C to send |
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139 ; |
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140 ; Uses Timer2 as a bit sync clock, sending out the next bit once we've hit 64 cycles on the timer |
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141 DMX_Bit: |
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142 ; Wait for bit sync clock |
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143 _dmx_bit_wait: |
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144 ; test OCA hit |
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145 sbic TIFR2, OCF2A |
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146 rjmp _dmx_bit_wait |
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147 |
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148 ;sbi LED_PORT, LED_BIT |
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149 |
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150 ; Output bit |
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151 ; XXX: ugly bit-testing, can't we do this using something more nifty? |
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152 brcs _dmx_bit_1 |
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153 |
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154 ; bit 0 |
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155 cbi DMX_PORT, DMX_DATA |
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156 rjmp _dmx_bit_done |
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157 |
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158 _dmx_bit_1: |
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159 ; bit 1 |
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160 sbi DMX_PORT, DMX_DATA |
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161 nop |
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162 |
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163 ; Bit sent |
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164 _dmx_bit_done: |
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165 ; reset OCA hit for next bit |
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166 cbi TIFR2, OCF2A |
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167 |
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168 ; OK, bit sync clock keeps running for next bit |
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169 ret |
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170 |
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171 ;; Bitbang one DMX byte out, using DMX_Bit |
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172 ;; r16: byte value |
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173 ; |
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174 ; Uses Timer2 as a bit sync clock; must call DMX_Frame_Start before first DMX_Frame |
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175 DMX_Frame: |
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176 ; Start bit |
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177 clc |
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178 rcall DMX_Bit |
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179 |
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180 ; Data bits: 8 |
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181 ldi r21, 8 |
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182 |
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183 _dmx_frame_loop: |
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184 ; shift + send bit |
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185 lsl r16 |
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186 rcall DMX_Bit |
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187 |
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188 ; loop |
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189 dec r21 |
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190 brne _dmx_frame_loop |
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191 |
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192 ; Stop bits |
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193 sec |
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194 rcall DMX_Bit |
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195 rcall DMX_Bit |
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196 |
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197 ; OK |
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198 ret |
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199 |
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200 ;; End of DMX frames |
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201 DMX_Frame_End: |
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202 ; Keep mark from end of last frame; DMX_Break_Start starts the break |
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203 ; Stop the timer |
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204 poke [DMX_TIMER_CRB, r20, (DMX_TIMER_WGM_2 << WGM22) | (DMX_TIMER_CS_STOP << CS20)] |
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205 |
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206 ; OK |
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207 ret |
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208 |
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209 ;; Send one value on all frames |
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210 ;; r17: byte value |
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211 DMX_Flood: |
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212 ; Break |
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213 rcall DMX_Break |
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214 |
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215 ; Start code |
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216 ldi r16, 0 |
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217 rcall DMX_Frame |
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218 |
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219 ; Channels |
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220 ; number of channels to send |
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221 ldi r22, 100 |
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222 |
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223 _dmx_flood_channels: |
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224 ; restore channel value |
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225 mov r16, r17 |
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226 |
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227 ; send channel value |
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228 rcall DMX_Frame |
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229 |
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230 ; loop |
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231 dec r22 |
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232 brne _dmx_flood_channels |
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233 |
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234 ; End packet |
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235 rcall DMX_Frame_End |
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236 |
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237 |
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238 ret |
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239 |
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240 ;; Program main |
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241 Main: |
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242 ; Initialization |
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243 ; Debug |
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244 sbi LED_DDR, LED_BIT |
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245 sbi LED_PORT, LED_BIT |
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246 |
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247 ; Stack |
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248 poke [SPL, r16:r17, RAMEND] |
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249 |
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250 ; Init |
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251 rcall DMX_Init |
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252 |
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253 cbi LED_PORT, LED_BIT |
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254 |
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255 ; Send; value |
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256 _main_loop: |
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257 ldi r17, 255 |
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258 rcall DMX_Flood |
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259 |
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260 cbi LED_PORT, LED_BIT |
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261 |
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262 ; never returns.. |
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263 rjmp _main_loop |
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264 |
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