hw.S
changeset 89 1b3cea759eff
parent 88 c923295ee520
child 90 13c2deb919d1
--- a/hw.S	Mon Jun 02 18:27:08 2014 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-.nolist
-.include "m168def.inc"      ; Same family as 328P
-.list
-
-; Interrupt vector
-.org 0x00
-        rjmp        main            ; Reset
-
-.org OC1Aaddr
-        rjmp        timer           ; Timer 1 Compare A 
-
-; Program code
-main:
-    ; Setup pins for output
-        sbi         DDRB, PORTB4        ; Out
-        sbi         DDRB, PORTB5        ; Out
-        
-    ; Flags for output
-        ldi         r16, (1 << PORTB4)
-
-    ; Setup Timer 0
-        ; Count to 64k
-        ldi         r18, HIGH(0xffff/2)
-        ldi         r19, LOW(0xffff/2)
-        sts         OCR1AH, r18
-        sts         OCR1AL, r19
- 
-        ; Normal port operation for both comperators
-        ; Bits WGM10:1 zero
-        ldi         r18,    0x00
-        sts         TCCR1A, r18
- 
-        ; CTC mode, 1/64 prescaled
-        ; the timer will start counting from now, but that shouldn't matter..
-        ldi         r18,    (1 << WGM12) | (0b011 << CS10)
-        sts         TCCR1B, r18
-       
-        ; Enable timer interrupt
-        ldi         r18, (1 << OCIE1A)
-        sts         TIMSK1, r18
-        
-        ; Setup sleep for Idle mode
-        ldi         r18, (0b000 << SM0) | (1 << SE)
-        sts         SMCR, r18
-
-        ; ...and enable interrupts
-        sei
-
-loop:
-        ; Flip
-        com         r16
-        
-        ; Output
-        out         PORTB, r16
-
-        ; Wait
-wait:   sleep
-        cpi         r20, 1
-        brne        wait
-        ldi         r20, 0
-
-        ; continue
-        rjmp loop
-
-; Counter overflow handler
-timer:
-        ; Set flag
-        ldi         r20, 1
-
-        ; Re-enable interrupts
-        reti
-