terom@1: ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
terom@1: ;***** Created: 2005-01-11 10:30 ******* Source: ATmega168.xml ***********
terom@1: ;*************************************************************************
terom@1: ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
terom@1: ;* 
terom@1: ;* Number            : AVR000
terom@1: ;* File Name         : "m168def.inc"
terom@1: ;* Title             : Register/Bit Definitions for the ATmega168
terom@1: ;* Date              : 2005-01-11
terom@1: ;* Version           : 2.14
terom@1: ;* Support E-mail    : avr@atmel.com
terom@1: ;* Target MCU        : ATmega168
terom@1: ;* 
terom@1: ;* DESCRIPTION
terom@1: ;* When including this file in the assembly program file, all I/O register 
terom@1: ;* names and I/O register bit names appearing in the data book can be used.
terom@1: ;* In addition, the six registers forming the three data pointers X, Y and 
terom@1: ;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
terom@1: ;* SRAM is also defined 
terom@1: ;* 
terom@1: ;* The Register names are represented by their hexadecimal address.
terom@1: ;* 
terom@1: ;* The Register Bit names are represented by their bit number (0-7).
terom@1: ;* 
terom@1: ;* Please observe the difference in using the bit names with instructions
terom@1: ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
terom@1: ;* (skip if bit in register set/cleared). The following example illustrates
terom@1: ;* this:
terom@1: ;* 
terom@1: ;* in    r16,PORTB             ;read PORTB latch
terom@1: ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
terom@1: ;* out   PORTB,r16             ;output to PORTB
terom@1: ;* 
terom@1: ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
terom@1: ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
terom@1: ;* rjmp  TOV0_is_set           ;jump if set
terom@1: ;* ...                         ;otherwise do something else
terom@1: ;*************************************************************************
terom@1: 
terom@1: ; #ifndef _M168DEF_INC_
terom@1: ; #define _M168DEF_INC_
terom@1: 
terom@1: 
terom@1: ; #pragma partinc 0
terom@1: 
terom@1: ; ***** SPECIFY DEVICE ***************************************************
terom@1: .device ATmega168
terom@1: ; #pragma AVRPART ADMIN PART_NAME ATmega168
terom@1: .equ	SIGNATURE_000	= 0x1e
terom@1: .equ	SIGNATURE_001	= 0x94
terom@1: .equ	SIGNATURE_002	= 0x06
terom@1: 
terom@1: ; #pragma AVRPART CORE CORE_VERSION V2E
terom@1: 
terom@1: 
terom@1: ; ***** I/O REGISTER DEFINITIONS *****************************************
terom@1: ; NOTE:
terom@1: ; Definitions marked "MEMORY MAPPED"are extended I/O ports
terom@1: ; and cannot be used with IN/OUT instructions
terom@1: .equ	UDR0	= 0xc6	; MEMORY MAPPED
terom@1: .equ	UBRR0H	= 0xc5	; MEMORY MAPPED
terom@1: .equ	UBRR0L	= 0xc4	; MEMORY MAPPED
terom@1: .equ	UCSR0C	= 0xc2	; MEMORY MAPPED
terom@1: .equ	UCSR0B	= 0xc1	; MEMORY MAPPED
terom@1: .equ	UCSR0A	= 0xc0	; MEMORY MAPPED
terom@1: .equ	TWAMR	= 0xbd	; MEMORY MAPPED
terom@1: .equ	TWCR	= 0xbc	; MEMORY MAPPED
terom@1: .equ	TWDR	= 0xbb	; MEMORY MAPPED
terom@1: .equ	TWAR	= 0xba	; MEMORY MAPPED
terom@1: .equ	TWSR	= 0xb9	; MEMORY MAPPED
terom@1: .equ	TWBR	= 0xb8	; MEMORY MAPPED
terom@1: .equ	ASSR	= 0xb6	; MEMORY MAPPED
terom@1: .equ	OCR2B	= 0xb4	; MEMORY MAPPED
terom@1: .equ	OCR2A	= 0xb3	; MEMORY MAPPED
terom@1: .equ	TCNT2	= 0xb2	; MEMORY MAPPED
terom@1: .equ	TCCR2B	= 0xb1	; MEMORY MAPPED
terom@1: .equ	TCCR2A	= 0xb0	; MEMORY MAPPED
terom@1: .equ	OCR1BH	= 0x8b	; MEMORY MAPPED
terom@1: .equ	OCR1BL	= 0x8a	; MEMORY MAPPED
terom@1: .equ	OCR1AH	= 0x89	; MEMORY MAPPED
terom@1: .equ	OCR1AL	= 0x88	; MEMORY MAPPED
terom@1: .equ	ICR1H	= 0x87	; MEMORY MAPPED
terom@1: .equ	ICR1L	= 0x86	; MEMORY MAPPED
terom@1: .equ	TCNT1H	= 0x85	; MEMORY MAPPED
terom@1: .equ	TCNT1L	= 0x84	; MEMORY MAPPED
terom@1: .equ	TCCR1C	= 0x82	; MEMORY MAPPED
terom@1: .equ	TCCR1B	= 0x81	; MEMORY MAPPED
terom@1: .equ	TCCR1A	= 0x80	; MEMORY MAPPED
terom@1: .equ	DIDR1	= 0x7f	; MEMORY MAPPED
terom@1: .equ	DIDR0	= 0x7e	; MEMORY MAPPED
terom@1: .equ	ADMUX	= 0x7c	; MEMORY MAPPED
terom@1: .equ	ADCSRB	= 0x7b	; MEMORY MAPPED
terom@1: .equ	ADCSRA	= 0x7a	; MEMORY MAPPED
terom@1: .equ	ADCH	= 0x79	; MEMORY MAPPED
terom@1: .equ	ADCL	= 0x78	; MEMORY MAPPED
terom@1: .equ	TIMSK2	= 0x70	; MEMORY MAPPED
terom@1: .equ	TIMSK1	= 0x6f	; MEMORY MAPPED
terom@1: .equ	TIMSK0	= 0x6e	; MEMORY MAPPED
terom@1: .equ	PCMSK2	= 0x6d	; MEMORY MAPPED
terom@1: .equ	PCMSK1	= 0x6c	; MEMORY MAPPED
terom@1: .equ	PCMSK0	= 0x6b	; MEMORY MAPPED
terom@1: .equ	EICRA	= 0x69	; MEMORY MAPPED
terom@1: .equ	PCICR	= 0x68	; MEMORY MAPPED
terom@1: .equ	OSCCAL	= 0x66	; MEMORY MAPPED
terom@1: .equ	PRR	= 0x64	; MEMORY MAPPED
terom@1: .equ	CLKPR	= 0x61	; MEMORY MAPPED
terom@1: .equ	WDTCSR	= 0x60	; MEMORY MAPPED
terom@1: .equ	SREG	= 0x3f
terom@1: .equ	SPH	= 0x3e
terom@1: .equ	SPL	= 0x3d
terom@1: .equ	SPMCSR	= 0x37
terom@1: .equ	MCUCR	= 0x35
terom@1: .equ	MCUSR	= 0x34
terom@1: .equ	SMCR	= 0x33
terom@1: .equ	ACSR	= 0x30
terom@1: .equ	SPDR	= 0x2e
terom@1: .equ	SPSR	= 0x2d
terom@1: .equ	SPCR	= 0x2c
terom@1: .equ	GPIOR2	= 0x2b
terom@1: .equ	GPIOR1	= 0x2a
terom@1: .equ	OCR0B	= 0x28
terom@1: .equ	OCR0A	= 0x27
terom@1: .equ	TCNT0	= 0x26
terom@1: .equ	TCCR0B	= 0x25
terom@1: .equ	TCCR0A	= 0x24
terom@1: .equ	GTCCR	= 0x23
terom@1: .equ	EEARH	= 0x22
terom@1: .equ	EEARL	= 0x21
terom@1: .equ	EEDR	= 0x20
terom@1: .equ	EECR	= 0x1f
terom@1: .equ	GPIOR0	= 0x1e
terom@1: .equ	EIMSK	= 0x1d
terom@1: .equ	EIFR	= 0x1c
terom@1: .equ	PCIFR	= 0x1b
terom@1: .equ	TIFR2	= 0x17
terom@1: .equ	TIFR1	= 0x16
terom@1: .equ	TIFR0	= 0x15
terom@1: .equ	PORTD	= 0x0b
terom@1: .equ	DDRD	= 0x0a
terom@1: .equ	PIND	= 0x09
terom@1: .equ	PORTC	= 0x08
terom@1: .equ	DDRC	= 0x07
terom@1: .equ	PINC	= 0x06
terom@1: .equ	PORTB	= 0x05
terom@1: .equ	DDRB	= 0x04
terom@1: .equ	PINB	= 0x03
terom@1: 
terom@1: 
terom@1: ; ***** BIT DEFINITIONS **************************************************
terom@1: 
terom@1: ; ***** USART0 ***********************
terom@1: ; UDR0 - USART I/O Data Register
terom@1: .equ	UDR0_0	= 0	; USART I/O Data Register bit 0
terom@1: .equ	UDR0_1	= 1	; USART I/O Data Register bit 1
terom@1: .equ	UDR0_2	= 2	; USART I/O Data Register bit 2
terom@1: .equ	UDR0_3	= 3	; USART I/O Data Register bit 3
terom@1: .equ	UDR0_4	= 4	; USART I/O Data Register bit 4
terom@1: .equ	UDR0_5	= 5	; USART I/O Data Register bit 5
terom@1: .equ	UDR0_6	= 6	; USART I/O Data Register bit 6
terom@1: .equ	UDR0_7	= 7	; USART I/O Data Register bit 7
terom@1: 
terom@1: ; UCSR0A - USART Control and Status Register A
terom@1: .equ	MPCM0	= 0	; Multi-processor Communication Mode
terom@1: .equ	U2X0	= 1	; Double the USART transmission speed
terom@1: .equ	UPE0	= 2	; Parity Error
terom@1: .equ	DOR0	= 3	; Data overRun
terom@1: .equ	FE0	= 4	; Framing Error
terom@1: .equ	UDRE0	= 5	; USART Data Register Empty
terom@1: .equ	TXC0	= 6	; USART Transmitt Complete
terom@1: .equ	RXC0	= 7	; USART Receive Complete
terom@1: 
terom@1: ; UCSR0B - USART Control and Status Register B
terom@1: .equ	TXB80	= 0	; Transmit Data Bit 8
terom@1: .equ	RXB80	= 1	; Receive Data Bit 8
terom@1: .equ	UCSZ02	= 2	; Character Size
terom@1: .equ	TXEN0	= 3	; Transmitter Enable
terom@1: .equ	RXEN0	= 4	; Receiver Enable
terom@1: .equ	UDRIE0	= 5	; USART Data register Empty Interrupt Enable
terom@1: .equ	TXCIE0	= 6	; TX Complete Interrupt Enable
terom@1: .equ	RXCIE0	= 7	; RX Complete Interrupt Enable
terom@1: 
terom@1: ; UCSR0C - USART Control and Status Register C
terom@1: .equ	UCPOL0	= 0	; Clock Polarity
terom@1: .equ	UCSZ00	= 1	; Character Size
terom@1: .equ	UCPHA0	= UCSZ00	; For compatibility
terom@1: .equ	UCSZ01	= 2	; Character Size
terom@1: .equ	UDORD0	= UCSZ01	; For compatibility
terom@1: .equ	USBS0	= 3	; Stop Bit Select
terom@1: .equ	UPM00	= 4	; Parity Mode Bit 0
terom@1: .equ	UPM01	= 5	; Parity Mode Bit 1
terom@1: .equ	UMSEL00	= 6	; USART Mode Select
terom@1: .equ	UMSEL0	= UMSEL00	; For compatibility
terom@1: .equ	UMSEL01	= 7	; USART Mode Select
terom@1: .equ	UMSEL1	= UMSEL01	; For compatibility
terom@1: 
terom@1: 
terom@1: ; ***** TWI **************************
terom@1: ; TWAMR - TWI (Slave) Address Mask Register
terom@1: .equ	TWAM0	= 1	; 
terom@1: .equ	TWAMR0	= TWAM0	; For compatibility
terom@1: .equ	TWAM1	= 2	; 
terom@1: .equ	TWAMR1	= TWAM1	; For compatibility
terom@1: .equ	TWAM2	= 3	; 
terom@1: .equ	TWAMR2	= TWAM2	; For compatibility
terom@1: .equ	TWAM3	= 4	; 
terom@1: .equ	TWAMR3	= TWAM3	; For compatibility
terom@1: .equ	TWAM4	= 5	; 
terom@1: .equ	TWAMR4	= TWAM4	; For compatibility
terom@1: .equ	TWAM5	= 6	; 
terom@1: .equ	TWAMR5	= TWAM5	; For compatibility
terom@1: .equ	TWAM6	= 7	; 
terom@1: .equ	TWAMR6	= TWAM6	; For compatibility
terom@1: 
terom@1: ; TWBR - TWI Bit Rate register
terom@1: .equ	TWBR0	= 0	; 
terom@1: .equ	TWBR1	= 1	; 
terom@1: .equ	TWBR2	= 2	; 
terom@1: .equ	TWBR3	= 3	; 
terom@1: .equ	TWBR4	= 4	; 
terom@1: .equ	TWBR5	= 5	; 
terom@1: .equ	TWBR6	= 6	; 
terom@1: .equ	TWBR7	= 7	; 
terom@1: 
terom@1: ; TWCR - TWI Control Register
terom@1: .equ	TWIE	= 0	; TWI Interrupt Enable
terom@1: .equ	TWEN	= 2	; TWI Enable Bit
terom@1: .equ	TWWC	= 3	; TWI Write Collition Flag
terom@1: .equ	TWSTO	= 4	; TWI Stop Condition Bit
terom@1: .equ	TWSTA	= 5	; TWI Start Condition Bit
terom@1: .equ	TWEA	= 6	; TWI Enable Acknowledge Bit
terom@1: .equ	TWINT	= 7	; TWI Interrupt Flag
terom@1: 
terom@1: ; TWSR - TWI Status Register
terom@1: .equ	TWPS0	= 0	; TWI Prescaler
terom@1: .equ	TWPS1	= 1	; TWI Prescaler
terom@1: .equ	TWS3	= 3	; TWI Status
terom@1: .equ	TWS4	= 4	; TWI Status
terom@1: .equ	TWS5	= 5	; TWI Status
terom@1: .equ	TWS6	= 6	; TWI Status
terom@1: .equ	TWS7	= 7	; TWI Status
terom@1: 
terom@1: ; TWDR - TWI Data register
terom@1: .equ	TWD0	= 0	; TWI Data Register Bit 0
terom@1: .equ	TWD1	= 1	; TWI Data Register Bit 1
terom@1: .equ	TWD2	= 2	; TWI Data Register Bit 2
terom@1: .equ	TWD3	= 3	; TWI Data Register Bit 3
terom@1: .equ	TWD4	= 4	; TWI Data Register Bit 4
terom@1: .equ	TWD5	= 5	; TWI Data Register Bit 5
terom@1: .equ	TWD6	= 6	; TWI Data Register Bit 6
terom@1: .equ	TWD7	= 7	; TWI Data Register Bit 7
terom@1: 
terom@1: ; TWAR - TWI (Slave) Address register
terom@1: .equ	TWGCE	= 0	; TWI General Call Recognition Enable Bit
terom@1: .equ	TWA0	= 1	; TWI (Slave) Address register Bit 0
terom@1: .equ	TWA1	= 2	; TWI (Slave) Address register Bit 1
terom@1: .equ	TWA2	= 3	; TWI (Slave) Address register Bit 2
terom@1: .equ	TWA3	= 4	; TWI (Slave) Address register Bit 3
terom@1: .equ	TWA4	= 5	; TWI (Slave) Address register Bit 4
terom@1: .equ	TWA5	= 6	; TWI (Slave) Address register Bit 5
terom@1: .equ	TWA6	= 7	; TWI (Slave) Address register Bit 6
terom@1: 
terom@1: 
terom@1: ; ***** TIMER_COUNTER_1 **************
terom@1: ; TIMSK1 - Timer/Counter Interrupt Mask Register
terom@1: .equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
terom@1: .equ	OCIE1A	= 1	; Timer/Counter1 Output CompareA Match Interrupt Enable
terom@1: .equ	OCIE1B	= 2	; Timer/Counter1 Output CompareB Match Interrupt Enable
terom@1: .equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
terom@1: 
terom@1: ; TIFR1 - Timer/Counter Interrupt Flag register
terom@1: .equ	TOV1	= 0	; Timer/Counter1 Overflow Flag
terom@1: .equ	OCF1A	= 1	; Output Compare Flag 1A
terom@1: .equ	OCF1B	= 2	; Output Compare Flag 1B
terom@1: .equ	ICF1	= 5	; Input Capture Flag 1
terom@1: 
terom@1: ; TCCR1A - Timer/Counter1 Control Register A
terom@1: .equ	WGM10	= 0	; Waveform Generation Mode
terom@1: .equ	WGM11	= 1	; Waveform Generation Mode
terom@1: .equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
terom@1: .equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
terom@1: .equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
terom@1: .equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
terom@1: 
terom@1: ; TCCR1B - Timer/Counter1 Control Register B
terom@1: .equ	CS10	= 0	; Prescaler source of Timer/Counter 1
terom@1: .equ	CS11	= 1	; Prescaler source of Timer/Counter 1
terom@1: .equ	CS12	= 2	; Prescaler source of Timer/Counter 1
terom@1: .equ	WGM12	= 3	; Waveform Generation Mode
terom@1: .equ	WGM13	= 4	; Waveform Generation Mode
terom@1: .equ	ICES1	= 6	; Input Capture 1 Edge Select
terom@1: .equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
terom@1: 
terom@1: ; TCCR1C - Timer/Counter1 Control Register C
terom@1: .equ	FOC1B	= 6	; 
terom@1: .equ	FOC1A	= 7	; 
terom@1: 
terom@1: ; GTCCR - General Timer/Counter Control Register
terom@1: .equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
terom@1: .equ	TSM	= 7	; Timer/Counter Synchronization Mode
terom@1: 
terom@1: 
terom@1: ; ***** TIMER_COUNTER_2 **************
terom@1: ; TIMSK2 - Timer/Counter Interrupt Mask register
terom@1: .equ	TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable
terom@1: .equ	TOIE2A	= TOIE2	; For compatibility
terom@1: .equ	OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable
terom@1: .equ	OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable
terom@1: 
terom@1: ; TIFR2 - Timer/Counter Interrupt Flag Register
terom@1: .equ	TOV2	= 0	; Timer/Counter2 Overflow Flag
terom@1: .equ	OCF2A	= 1	; Output Compare Flag 2A
terom@1: .equ	OCF2B	= 2	; Output Compare Flag 2B
terom@1: 
terom@1: ; TCCR2A - Timer/Counter2 Control Register A
terom@1: .equ	WGM20	= 0	; Waveform Genration Mode
terom@1: .equ	WGM21	= 1	; Waveform Genration Mode
terom@1: .equ	COM2B0	= 4	; Compare Output Mode bit 0
terom@1: .equ	COM2B1	= 5	; Compare Output Mode bit 1
terom@1: .equ	COM2A0	= 6	; Compare Output Mode bit 1
terom@1: .equ	COM2A1	= 7	; Compare Output Mode bit 1
terom@1: 
terom@1: ; TCCR2B - Timer/Counter2 Control Register B
terom@1: .equ	CS20	= 0	; Clock Select bit 0
terom@1: .equ	CS21	= 1	; Clock Select bit 1
terom@1: .equ	CS22	= 2	; Clock Select bit 2
terom@1: .equ	WGM22	= 3	; Waveform Generation Mode
terom@1: .equ	FOC2B	= 6	; Force Output Compare B
terom@1: .equ	FOC2A	= 7	; Force Output Compare A
terom@1: 
terom@1: ; TCNT2 - Timer/Counter2
terom@1: .equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0
terom@1: .equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1
terom@1: .equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2
terom@1: .equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3
terom@1: .equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4
terom@1: .equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5
terom@1: .equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6
terom@1: .equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7
terom@1: 
terom@1: ; OCR2A - Timer/Counter2 Output Compare Register A
terom@1: .equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
terom@1: .equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
terom@1: .equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
terom@1: .equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
terom@1: .equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
terom@1: .equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
terom@1: .equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
terom@1: .equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
terom@1: 
terom@1: ; OCR2B - Timer/Counter2 Output Compare Register B
terom@1: ;.equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
terom@1: ;.equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
terom@1: ;.equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
terom@1: ;.equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
terom@1: ;.equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
terom@1: ;.equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
terom@1: ;.equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
terom@1: ;.equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
terom@1: 
terom@1: ; ASSR - Asynchronous Status Register
terom@1: .equ	TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy
terom@1: .equ	TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy
terom@1: .equ	OCR2BUB	= 2	; Output Compare Register 2 Update Busy
terom@1: .equ	OCR2AUB	= 3	; Output Compare Register2 Update Busy
terom@1: .equ	TCN2UB	= 4	; Timer/Counter2 Update Busy
terom@1: .equ	AS2	= 5	; Asynchronous Timer/Counter2
terom@1: .equ	EXCLK	= 6	; Enable External Clock Input
terom@1: 
terom@1: ; GTCCR - General Timer Counter Control register
terom@1: .equ	PSRASY	= 1	; Prescaler Reset Timer/Counter2
terom@1: .equ	PSR2	= PSRASY	; For compatibility
terom@1: ;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
terom@1: 
terom@1: 
terom@1: ; ***** AD_CONVERTER *****************
terom@1: ; ADMUX - The ADC multiplexer Selection Register
terom@1: .equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
terom@1: .equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
terom@1: .equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
terom@1: .equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
terom@1: .equ	ADLAR	= 5	; Left Adjust Result
terom@1: .equ	REFS0	= 6	; Reference Selection Bit 0
terom@1: .equ	REFS1	= 7	; Reference Selection Bit 1
terom@1: 
terom@1: ; ADCSRA - The ADC Control and Status register A
terom@1: .equ	ADPS0	= 0	; ADC  Prescaler Select Bits
terom@1: .equ	ADPS1	= 1	; ADC  Prescaler Select Bits
terom@1: .equ	ADPS2	= 2	; ADC  Prescaler Select Bits
terom@1: .equ	ADIE	= 3	; ADC Interrupt Enable
terom@1: .equ	ADIF	= 4	; ADC Interrupt Flag
terom@1: .equ	ADATE	= 5	; ADC  Auto Trigger Enable
terom@1: .equ	ADSC	= 6	; ADC Start Conversion
terom@1: .equ	ADEN	= 7	; ADC Enable
terom@1: 
terom@1: ; ADCSRB - The ADC Control and Status register B
terom@1: .equ	ADTS0	= 0	; ADC Auto Trigger Source bit 0
terom@1: .equ	ADTS1	= 1	; ADC Auto Trigger Source bit 1
terom@1: .equ	ADTS2	= 2	; ADC Auto Trigger Source bit 2
terom@1: .equ	ACME	= 6	; 
terom@1: 
terom@1: ; ADCH - ADC Data Register High Byte
terom@1: .equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
terom@1: .equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
terom@1: .equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
terom@1: .equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
terom@1: .equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
terom@1: .equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
terom@1: .equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
terom@1: .equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
terom@1: 
terom@1: ; ADCL - ADC Data Register Low Byte
terom@1: .equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
terom@1: .equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
terom@1: .equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
terom@1: .equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
terom@1: .equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
terom@1: .equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
terom@1: .equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
terom@1: .equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
terom@1: 
terom@1: ; DIDR0 - Digital Input Disable Register
terom@1: .equ	ADC0D	= 0	; 
terom@1: .equ	ADC1D	= 1	; 
terom@1: .equ	ADC2D	= 2	; 
terom@1: .equ	ADC3D	= 3	; 
terom@1: .equ	ADC4D	= 4	; 
terom@1: .equ	ADC5D	= 5	; 
terom@1: 
terom@1: 
terom@1: ; ***** ANALOG_COMPARATOR ************
terom@1: ; ACSR - Analog Comparator Control And Status Register
terom@1: .equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
terom@1: .equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
terom@1: .equ	ACIC	= 2	; 
terom@1: .equ	ACIE	= 3	; Analog Comparator Interrupt Enable
terom@1: .equ	ACI	= 4	; Analog Comparator Interrupt Flag
terom@1: .equ	ACO	= 5	; Analog Compare Output
terom@1: .equ	ACBG	= 6	; Analog Comparator Bandgap Select
terom@1: .equ	ACD	= 7	; Analog Comparator Disable
terom@1: 
terom@1: ; DIDR1 - Digital Input Disable Register 1
terom@1: .equ	AIN0D	= 0	; AIN0 Digital Input Disable
terom@1: .equ	AIN1D	= 1	; AIN1 Digital Input Disable
terom@1: 
terom@1: 
terom@1: ; ***** PORTB ************************
terom@1: ; PORTB - Port B Data Register
terom@1: .equ	PORTB0	= 0	; Port B Data Register bit 0
terom@1: .equ	PB0	= 0	; For compatibility
terom@1: .equ	PORTB1	= 1	; Port B Data Register bit 1
terom@1: .equ	PB1	= 1	; For compatibility
terom@1: .equ	PORTB2	= 2	; Port B Data Register bit 2
terom@1: .equ	PB2	= 2	; For compatibility
terom@1: .equ	PORTB3	= 3	; Port B Data Register bit 3
terom@1: .equ	PB3	= 3	; For compatibility
terom@1: .equ	PORTB4	= 4	; Port B Data Register bit 4
terom@1: .equ	PB4	= 4	; For compatibility
terom@1: .equ	PORTB5	= 5	; Port B Data Register bit 5
terom@1: .equ	PB5	= 5	; For compatibility
terom@1: .equ	PORTB6	= 6	; Port B Data Register bit 6
terom@1: .equ	PB6	= 6	; For compatibility
terom@1: .equ	PORTB7	= 7	; Port B Data Register bit 7
terom@1: .equ	PB7	= 7	; For compatibility
terom@1: 
terom@1: ; DDRB - Port B Data Direction Register
terom@1: .equ	DDB0	= 0	; Port B Data Direction Register bit 0
terom@1: .equ	DDB1	= 1	; Port B Data Direction Register bit 1
terom@1: .equ	DDB2	= 2	; Port B Data Direction Register bit 2
terom@1: .equ	DDB3	= 3	; Port B Data Direction Register bit 3
terom@1: .equ	DDB4	= 4	; Port B Data Direction Register bit 4
terom@1: .equ	DDB5	= 5	; Port B Data Direction Register bit 5
terom@1: .equ	DDB6	= 6	; Port B Data Direction Register bit 6
terom@1: .equ	DDB7	= 7	; Port B Data Direction Register bit 7
terom@1: 
terom@1: ; PINB - Port B Input Pins
terom@1: .equ	PINB0	= 0	; Port B Input Pins bit 0
terom@1: .equ	PINB1	= 1	; Port B Input Pins bit 1
terom@1: .equ	PINB2	= 2	; Port B Input Pins bit 2
terom@1: .equ	PINB3	= 3	; Port B Input Pins bit 3
terom@1: .equ	PINB4	= 4	; Port B Input Pins bit 4
terom@1: .equ	PINB5	= 5	; Port B Input Pins bit 5
terom@1: .equ	PINB6	= 6	; Port B Input Pins bit 6
terom@1: .equ	PINB7	= 7	; Port B Input Pins bit 7
terom@1: 
terom@1: 
terom@1: ; ***** PORTC ************************
terom@1: ; PORTC - Port C Data Register
terom@1: .equ	PORTC0	= 0	; Port C Data Register bit 0
terom@1: .equ	PC0	= 0	; For compatibility
terom@1: .equ	PORTC1	= 1	; Port C Data Register bit 1
terom@1: .equ	PC1	= 1	; For compatibility
terom@1: .equ	PORTC2	= 2	; Port C Data Register bit 2
terom@1: .equ	PC2	= 2	; For compatibility
terom@1: .equ	PORTC3	= 3	; Port C Data Register bit 3
terom@1: .equ	PC3	= 3	; For compatibility
terom@1: .equ	PORTC4	= 4	; Port C Data Register bit 4
terom@1: .equ	PC4	= 4	; For compatibility
terom@1: .equ	PORTC5	= 5	; Port C Data Register bit 5
terom@1: .equ	PC5	= 5	; For compatibility
terom@1: .equ	PORTC6	= 6	; Port C Data Register bit 6
terom@1: .equ	PC6	= 6	; For compatibility
terom@1: 
terom@1: ; DDRC - Port C Data Direction Register
terom@1: .equ	DDC0	= 0	; Port C Data Direction Register bit 0
terom@1: .equ	DDC1	= 1	; Port C Data Direction Register bit 1
terom@1: .equ	DDC2	= 2	; Port C Data Direction Register bit 2
terom@1: .equ	DDC3	= 3	; Port C Data Direction Register bit 3
terom@1: .equ	DDC4	= 4	; Port C Data Direction Register bit 4
terom@1: .equ	DDC5	= 5	; Port C Data Direction Register bit 5
terom@1: .equ	DDC6	= 6	; Port C Data Direction Register bit 6
terom@1: 
terom@1: ; PINC - Port C Input Pins
terom@1: .equ	PINC0	= 0	; Port C Input Pins bit 0
terom@1: .equ	PINC1	= 1	; Port C Input Pins bit 1
terom@1: .equ	PINC2	= 2	; Port C Input Pins bit 2
terom@1: .equ	PINC3	= 3	; Port C Input Pins bit 3
terom@1: .equ	PINC4	= 4	; Port C Input Pins bit 4
terom@1: .equ	PINC5	= 5	; Port C Input Pins bit 5
terom@1: .equ	PINC6	= 6	; Port C Input Pins bit 6
terom@1: 
terom@1: 
terom@1: ; ***** PORTD ************************
terom@1: ; PORTD - Port D Data Register
terom@1: .equ	PORTD0	= 0	; Port D Data Register bit 0
terom@1: .equ	PD0	= 0	; For compatibility
terom@1: .equ	PORTD1	= 1	; Port D Data Register bit 1
terom@1: .equ	PD1	= 1	; For compatibility
terom@1: .equ	PORTD2	= 2	; Port D Data Register bit 2
terom@1: .equ	PD2	= 2	; For compatibility
terom@1: .equ	PORTD3	= 3	; Port D Data Register bit 3
terom@1: .equ	PD3	= 3	; For compatibility
terom@1: .equ	PORTD4	= 4	; Port D Data Register bit 4
terom@1: .equ	PD4	= 4	; For compatibility
terom@1: .equ	PORTD5	= 5	; Port D Data Register bit 5
terom@1: .equ	PD5	= 5	; For compatibility
terom@1: .equ	PORTD6	= 6	; Port D Data Register bit 6
terom@1: .equ	PD6	= 6	; For compatibility
terom@1: .equ	PORTD7	= 7	; Port D Data Register bit 7
terom@1: .equ	PD7	= 7	; For compatibility
terom@1: 
terom@1: ; DDRD - Port D Data Direction Register
terom@1: .equ	DDD0	= 0	; Port D Data Direction Register bit 0
terom@1: .equ	DDD1	= 1	; Port D Data Direction Register bit 1
terom@1: .equ	DDD2	= 2	; Port D Data Direction Register bit 2
terom@1: .equ	DDD3	= 3	; Port D Data Direction Register bit 3
terom@1: .equ	DDD4	= 4	; Port D Data Direction Register bit 4
terom@1: .equ	DDD5	= 5	; Port D Data Direction Register bit 5
terom@1: .equ	DDD6	= 6	; Port D Data Direction Register bit 6
terom@1: .equ	DDD7	= 7	; Port D Data Direction Register bit 7
terom@1: 
terom@1: ; PIND - Port D Input Pins
terom@1: .equ	PIND0	= 0	; Port D Input Pins bit 0
terom@1: .equ	PIND1	= 1	; Port D Input Pins bit 1
terom@1: .equ	PIND2	= 2	; Port D Input Pins bit 2
terom@1: .equ	PIND3	= 3	; Port D Input Pins bit 3
terom@1: .equ	PIND4	= 4	; Port D Input Pins bit 4
terom@1: .equ	PIND5	= 5	; Port D Input Pins bit 5
terom@1: .equ	PIND6	= 6	; Port D Input Pins bit 6
terom@1: .equ	PIND7	= 7	; Port D Input Pins bit 7
terom@1: 
terom@1: 
terom@1: ; ***** TIMER_COUNTER_0 **************
terom@1: ; TIMSK0 - Timer/Counter0 Interrupt Mask Register
terom@1: .equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
terom@1: .equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
terom@1: .equ	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable
terom@1: 
terom@1: ; TIFR0 - Timer/Counter0 Interrupt Flag register
terom@1: .equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
terom@1: .equ	OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
terom@1: .equ	OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B
terom@1: 
terom@1: ; TCCR0A - Timer/Counter  Control Register A
terom@1: .equ	WGM00	= 0	; Waveform Generation Mode
terom@1: .equ	WGM01	= 1	; Waveform Generation Mode
terom@1: .equ	COM0B0	= 4	; Compare Output Mode, Fast PWm
terom@1: .equ	COM0B1	= 5	; Compare Output Mode, Fast PWm
terom@1: .equ	COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
terom@1: .equ	COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode
terom@1: 
terom@1: ; TCCR0B - Timer/Counter Control Register B
terom@1: .equ	CS00	= 0	; Clock Select
terom@1: .equ	CS01	= 1	; Clock Select
terom@1: .equ	CS02	= 2	; Clock Select
terom@1: .equ	WGM02	= 3	; 
terom@1: .equ	FOC0B	= 6	; Force Output Compare B
terom@1: .equ	FOC0A	= 7	; Force Output Compare A
terom@1: 
terom@1: ; TCNT0 - Timer/Counter0
terom@1: .equ	TCNT0_0	= 0	; 
terom@1: .equ	TCNT0_1	= 1	; 
terom@1: .equ	TCNT0_2	= 2	; 
terom@1: .equ	TCNT0_3	= 3	; 
terom@1: .equ	TCNT0_4	= 4	; 
terom@1: .equ	TCNT0_5	= 5	; 
terom@1: .equ	TCNT0_6	= 6	; 
terom@1: .equ	TCNT0_7	= 7	; 
terom@1: 
terom@1: ; OCR0A - Timer/Counter0 Output Compare Register
terom@1: .equ	OCROA_0	= 0	; 
terom@1: .equ	OCROA_1	= 1	; 
terom@1: .equ	OCROA_2	= 2	; 
terom@1: .equ	OCROA_3	= 3	; 
terom@1: .equ	OCROA_4	= 4	; 
terom@1: .equ	OCROA_5	= 5	; 
terom@1: .equ	OCROA_6	= 6	; 
terom@1: .equ	OCROA_7	= 7	; 
terom@1: 
terom@1: ; OCR0B - Timer/Counter0 Output Compare Register
terom@1: .equ	OCR0B_0	= 0	; 
terom@1: .equ	OCR0B_1	= 1	; 
terom@1: .equ	OCR0B_2	= 2	; 
terom@1: .equ	OCR0B_3	= 3	; 
terom@1: .equ	OCR0B_4	= 4	; 
terom@1: .equ	OCR0B_5	= 5	; 
terom@1: .equ	OCR0B_6	= 6	; 
terom@1: .equ	OCR0B_7	= 7	; 
terom@1: 
terom@1: ; GTCCR - General Timer/Counter Control Register
terom@1: ;.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
terom@1: .equ	PSR10	= PSRSYNC	; For compatibility
terom@1: ;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
terom@1: 
terom@1: 
terom@1: ; ***** EXTERNAL_INTERRUPT ***********
terom@1: ; EICRA - External Interrupt Control Register
terom@1: .equ	ISC00	= 0	; External Interrupt Sense Control 0 Bit 0
terom@1: .equ	ISC01	= 1	; External Interrupt Sense Control 0 Bit 1
terom@1: .equ	ISC10	= 2	; External Interrupt Sense Control 1 Bit 0
terom@1: .equ	ISC11	= 3	; External Interrupt Sense Control 1 Bit 1
terom@1: 
terom@1: ; EIMSK - External Interrupt Mask Register
terom@1: .equ	INT0	= 0	; External Interrupt Request 0 Enable
terom@1: .equ	INT1	= 1	; External Interrupt Request 1 Enable
terom@1: 
terom@1: ; EIFR - External Interrupt Flag Register
terom@1: .equ	INTF0	= 0	; External Interrupt Flag 0
terom@1: .equ	INTF1	= 1	; External Interrupt Flag 1
terom@1: 
terom@1: ; PCMSK2 - Pin Change Mask Register 2
terom@1: .equ	PCINT16	= 0	; Pin Change Enable Mask 16
terom@1: .equ	PCINT17	= 1	; Pin Change Enable Mask 17
terom@1: .equ	PCINT18	= 2	; Pin Change Enable Mask 18
terom@1: .equ	PCINT19	= 3	; Pin Change Enable Mask 19
terom@1: .equ	PCINT20	= 4	; Pin Change Enable Mask 20
terom@1: .equ	PCINT21	= 5	; Pin Change Enable Mask 21
terom@1: .equ	PCINT22	= 6	; Pin Change Enable Mask 22
terom@1: .equ	PCINT23	= 7	; Pin Change Enable Mask 23
terom@1: 
terom@1: ; PCMSK1 - Pin Change Mask Register 1
terom@1: .equ	PCINT8	= 0	; Pin Change Enable Mask 8
terom@1: .equ	PCINT9	= 1	; Pin Change Enable Mask 9
terom@1: .equ	PCINT10	= 2	; Pin Change Enable Mask 10
terom@1: .equ	PCINT11	= 3	; Pin Change Enable Mask 11
terom@1: .equ	PCINT12	= 4	; Pin Change Enable Mask 12
terom@1: .equ	PCINT13	= 5	; Pin Change Enable Mask 13
terom@1: .equ	PCINT14	= 6	; Pin Change Enable Mask 14
terom@1: 
terom@1: ; PCMSK0 - Pin Change Mask Register 0
terom@1: .equ	PCINT0	= 0	; Pin Change Enable Mask 0
terom@1: .equ	PCINT1	= 1	; Pin Change Enable Mask 1
terom@1: .equ	PCINT2	= 2	; Pin Change Enable Mask 2
terom@1: .equ	PCINT3	= 3	; Pin Change Enable Mask 3
terom@1: .equ	PCINT4	= 4	; Pin Change Enable Mask 4
terom@1: .equ	PCINT5	= 5	; Pin Change Enable Mask 5
terom@1: .equ	PCINT6	= 6	; Pin Change Enable Mask 6
terom@1: .equ	PCINT7	= 7	; Pin Change Enable Mask 7
terom@1: 
terom@1: ; PCIFR - Pin Change Interrupt Flag Register
terom@1: .equ	PCIF0	= 0	; Pin Change Interrupt Flag 0
terom@1: .equ	PCIF1	= 1	; Pin Change Interrupt Flag 1
terom@1: .equ	PCIF2	= 2	; Pin Change Interrupt Flag 2
terom@1: 
terom@1: 
terom@1: ; ***** SPI **************************
terom@1: ; SPDR - SPI Data Register
terom@1: .equ	SPDR0	= 0	; SPI Data Register bit 0
terom@1: .equ	SPDR1	= 1	; SPI Data Register bit 1
terom@1: .equ	SPDR2	= 2	; SPI Data Register bit 2
terom@1: .equ	SPDR3	= 3	; SPI Data Register bit 3
terom@1: .equ	SPDR4	= 4	; SPI Data Register bit 4
terom@1: .equ	SPDR5	= 5	; SPI Data Register bit 5
terom@1: .equ	SPDR6	= 6	; SPI Data Register bit 6
terom@1: .equ	SPDR7	= 7	; SPI Data Register bit 7
terom@1: 
terom@1: ; SPSR - SPI Status Register
terom@1: .equ	SPI2X	= 0	; Double SPI Speed Bit
terom@1: .equ	WCOL	= 6	; Write Collision Flag
terom@1: .equ	SPIF	= 7	; SPI Interrupt Flag
terom@1: 
terom@1: ; SPCR - SPI Control Register
terom@1: .equ	SPR0	= 0	; SPI Clock Rate Select 0
terom@1: .equ	SPR1	= 1	; SPI Clock Rate Select 1
terom@1: .equ	CPHA	= 2	; Clock Phase
terom@1: .equ	CPOL	= 3	; Clock polarity
terom@1: .equ	MSTR	= 4	; Master/Slave Select
terom@1: .equ	DORD	= 5	; Data Order
terom@1: .equ	SPE	= 6	; SPI Enable
terom@1: .equ	SPIE	= 7	; SPI Interrupt Enable
terom@1: 
terom@1: 
terom@1: ; ***** CPU **************************
terom@1: ; SREG - Status Register
terom@1: .equ	SREG_C	= 0	; Carry Flag
terom@1: .equ	SREG_Z	= 1	; Zero Flag
terom@1: .equ	SREG_N	= 2	; Negative Flag
terom@1: .equ	SREG_V	= 3	; Two's Complement Overflow Flag
terom@1: .equ	SREG_S	= 4	; Sign Bit
terom@1: .equ	SREG_H	= 5	; Half Carry Flag
terom@1: .equ	SREG_T	= 6	; Bit Copy Storage
terom@1: .equ	SREG_I	= 7	; Global Interrupt Enable
terom@1: 
terom@1: ; OSCCAL - Oscillator Calibration Value
terom@1: .equ	CAL0	= 0	; Oscillator Calibration Value Bit0
terom@1: .equ	CAL1	= 1	; Oscillator Calibration Value Bit1
terom@1: .equ	CAL2	= 2	; Oscillator Calibration Value Bit2
terom@1: .equ	CAL3	= 3	; Oscillator Calibration Value Bit3
terom@1: .equ	CAL4	= 4	; Oscillator Calibration Value Bit4
terom@1: .equ	CAL5	= 5	; Oscillator Calibration Value Bit5
terom@1: .equ	CAL6	= 6	; Oscillator Calibration Value Bit6
terom@1: .equ	CAL7	= 7	; Oscillator Calibration Value Bit7
terom@1: 
terom@1: ; CLKPR - Clock Prescale Register
terom@1: .equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
terom@1: .equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
terom@1: .equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
terom@1: .equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
terom@1: .equ	CLKPCE	= 7	; Clock Prescaler Change Enable
terom@1: 
terom@1: ; SPMCSR - Store Program Memory Control Register
terom@1: .equ	SELFPRGEN	= 0	; Self Programming Enable
terom@1: .equ	PGERS	= 1	; Page Erase
terom@1: .equ	PGWRT	= 2	; Page Write
terom@1: .equ	BLBSET	= 3	; Boot Lock Bit Set
terom@1: .equ	RWWSRE	= 4	; Read-While-Write section read enable
terom@1: .equ	RWWSB	= 6	; Read-While-Write Section Busy
terom@1: .equ	SPMIE	= 7	; SPM Interrupt Enable
terom@1: 
terom@1: ; MCUCR - MCU Control Register
terom@1: .equ	IVCE	= 0	; 
terom@1: .equ	IVSEL	= 1	; 
terom@1: .equ	PUD	= 4	; 
terom@1: 
terom@1: ; MCUSR - MCU Status Register
terom@1: .equ	PORF	= 0	; Power-on reset flag
terom@1: .equ	EXTRF	= 1	; External Reset Flag
terom@1: .equ	EXTREF	= EXTRF	; For compatibility
terom@1: .equ	BORF	= 2	; Brown-out Reset Flag
terom@1: .equ	WDRF	= 3	; Watchdog Reset Flag
terom@1: 
terom@1: ; SMCR - 
terom@1: .equ	SE	= 0	; 
terom@1: .equ	SM0	= 1	; 
terom@1: .equ	SM1	= 2	; 
terom@1: .equ	SM2	= 3	; 
terom@1: 
terom@1: ; GPIOR2 - General Purpose I/O Register 2
terom@1: .equ	GPIOR20	= 0	; 
terom@1: .equ	GPIOR21	= 1	; 
terom@1: .equ	GPIOR22	= 2	; 
terom@1: .equ	GPIOR23	= 3	; 
terom@1: .equ	GPIOR24	= 4	; 
terom@1: .equ	GPIOR25	= 5	; 
terom@1: .equ	GPIOR26	= 6	; 
terom@1: .equ	GPIOR27	= 7	; 
terom@1: 
terom@1: ; GPIOR1 - General Purpose I/O Register 1
terom@1: .equ	GPIOR10	= 0	; 
terom@1: .equ	GPIOR11	= 1	; 
terom@1: .equ	GPIOR12	= 2	; 
terom@1: .equ	GPIOR13	= 3	; 
terom@1: .equ	GPIOR14	= 4	; 
terom@1: .equ	GPIOR15	= 5	; 
terom@1: .equ	GPIOR16	= 6	; 
terom@1: .equ	GPIOR17	= 7	; 
terom@1: 
terom@1: ; GPIOR0 - General Purpose I/O Register 0
terom@1: .equ	GPIOR00	= 0	; 
terom@1: .equ	GPIOR01	= 1	; 
terom@1: .equ	GPIOR02	= 2	; 
terom@1: .equ	GPIOR03	= 3	; 
terom@1: .equ	GPIOR04	= 4	; 
terom@1: .equ	GPIOR05	= 5	; 
terom@1: .equ	GPIOR06	= 6	; 
terom@1: .equ	GPIOR07	= 7	; 
terom@1: 
terom@1: ; PRR - Power Reduction Register
terom@1: .equ	PRADC	= 0	; Power Reduction ADC
terom@1: .equ	PRUSART0	= 1	; Power Reduction USART
terom@1: .equ	PRSPI	= 2	; Power Reduction Serial Peripheral Interface
terom@1: .equ	PRTIM1	= 3	; Power Reduction Timer/Counter1
terom@1: .equ	PRTIM0	= 5	; Power Reduction Timer/Counter0
terom@1: .equ	PRTIM2	= 6	; Power Reduction Timer/Counter2
terom@1: .equ	PRTWI	= 7	; Power Reduction TWI
terom@1: 
terom@1: ; PCICR - 
terom@1: .equ	PCIE0	= 0	; 
terom@1: .equ	PCIE1	= 1	; 
terom@1: .equ	PCIE2	= 2	; 
terom@1: 
terom@1: 
terom@1: ; ***** WATCHDOG *********************
terom@1: ; WDTCSR - Watchdog Timer Control Register
terom@1: .equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
terom@1: .equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
terom@1: .equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
terom@1: .equ	WDE	= 3	; Watch Dog Enable
terom@1: .equ	WDCE	= 4	; Watchdog Change Enable
terom@1: .equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
terom@1: .equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
terom@1: .equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag
terom@1: 
terom@1: 
terom@1: ; ***** EEPROM ***********************
terom@1: ; EEARL - EEPROM Address Register Low Byte
terom@1: .equ	EEAR0	= 0	; EEPROM Read/Write Access Bit 0
terom@1: .equ	EEAR1	= 1	; EEPROM Read/Write Access Bit 1
terom@1: .equ	EEAR2	= 2	; EEPROM Read/Write Access Bit 2
terom@1: .equ	EEAR3	= 3	; EEPROM Read/Write Access Bit 3
terom@1: .equ	EEAR4	= 4	; EEPROM Read/Write Access Bit 4
terom@1: .equ	EEAR5	= 5	; EEPROM Read/Write Access Bit 5
terom@1: .equ	EEAR6	= 6	; EEPROM Read/Write Access Bit 6
terom@1: .equ	EEAR7	= 7	; EEPROM Read/Write Access Bit 7
terom@1: 
terom@1: ; EEARH - EEPROM Address Register High Byte
terom@1: .equ	EEAR8	= 0	; EEPROM Read/Write Access Bit 0
terom@1: 
terom@1: ; EEDR - EEPROM Data Register
terom@1: .equ	EEDR0	= 0	; EEPROM Data Register bit 0
terom@1: .equ	EEDR1	= 1	; EEPROM Data Register bit 1
terom@1: .equ	EEDR2	= 2	; EEPROM Data Register bit 2
terom@1: .equ	EEDR3	= 3	; EEPROM Data Register bit 3
terom@1: .equ	EEDR4	= 4	; EEPROM Data Register bit 4
terom@1: .equ	EEDR5	= 5	; EEPROM Data Register bit 5
terom@1: .equ	EEDR6	= 6	; EEPROM Data Register bit 6
terom@1: .equ	EEDR7	= 7	; EEPROM Data Register bit 7
terom@1: 
terom@1: ; EECR - EEPROM Control Register
terom@1: .equ	EERE	= 0	; EEPROM Read Enable
terom@1: .equ	EEPE	= 1	; EEPROM Write Enable
terom@1: .equ	EEMPE	= 2	; EEPROM Master Write Enable
terom@1: .equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
terom@1: .equ	EEPM0	= 4	; EEPROM Programming Mode Bit 0
terom@1: .equ	EEPM1	= 5	; EEPROM Programming Mode Bit 1
terom@1: 
terom@1: 
terom@1: 
terom@1: ; ***** LOCKSBITS ********************************************************
terom@1: .equ	LB1	= 0	; Lock bit
terom@1: .equ	LB2	= 1	; Lock bit
terom@1: .equ	BLB01	= 2	; Boot Lock bit
terom@1: .equ	BLB02	= 3	; Boot Lock bit
terom@1: .equ	BLB11	= 4	; Boot lock bit
terom@1: .equ	BLB12	= 5	; Boot lock bit
terom@1: 
terom@1: 
terom@1: ; ***** FUSES ************************************************************
terom@1: ; LOW fuse bits
terom@1: .equ	CKSEL0	= 0	; Select Clock Source
terom@1: .equ	CKSEL1	= 1	; Select Clock Source
terom@1: .equ	CKSEL2	= 2	; Select Clock Source
terom@1: .equ	CKSEL3	= 3	; Select Clock Source
terom@1: .equ	SUT0	= 4	; Select start-up time
terom@1: .equ	SUT1	= 5	; Select start-up time
terom@1: .equ	CKOUT	= 6	; Clock output
terom@1: .equ	CKDIV8	= 7	; Divide clock by 8
terom@1: 
terom@1: ; HIGH fuse bits
terom@1: .equ	BODLEVEL0	= 0	; Brown-out Detector trigger level
terom@1: .equ	BODLEVEL1	= 1	; Brown-out Detector trigger level
terom@1: .equ	BODLEVEL2	= 2	; Brown-out Detector trigger level
terom@1: .equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
terom@1: .equ	WDTON	= 4	; Watchdog Timer Always On
terom@1: .equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
terom@1: .equ	DWEN	= 6	; debugWIRE Enable
terom@1: .equ	RSTDISBL	= 7	; External reset disable
terom@1: 
terom@1: ; EXTENDED fuse bits
terom@1: .equ	BOOTRST	= 0	; Select reset vector
terom@1: .equ	BOOTSZ0	= 1	; Select boot size
terom@1: .equ	BOOTSZ1	= 2	; Select boot size
terom@1: 
terom@1: 
terom@1: 
terom@1: ; ***** CPU REGISTER DEFINITIONS *****************************************
terom@1: .def	XH	= r27
terom@1: .def	XL	= r26
terom@1: .def	YH	= r29
terom@1: .def	YL	= r28
terom@1: .def	ZH	= r31
terom@1: .def	ZL	= r30
terom@1: 
terom@1: 
terom@1: 
terom@1: ; ***** DATA MEMORY DECLARATIONS *****************************************
terom@1: .equ	FLASHEND	= 0x1fff	; Note: Word address
terom@1: .equ	IOEND	= 0x00ff
terom@1: .equ	SRAM_START	= 0x0100
terom@1: .equ	SRAM_SIZE	= 1024
terom@1: .equ	RAMEND	= 0x04ff
terom@1: .equ	XRAMEND	= 0x0000
terom@1: .equ	E2END	= 0x01ff
terom@1: .equ	EEPROMEND	= 0x01ff
terom@1: .equ	EEADRBITS	= 9
terom@1: ; #pragma AVRPART MEMORY PROG_FLASH 16384
terom@1: ; #pragma AVRPART MEMORY EEPROM 512
terom@1: ; #pragma AVRPART MEMORY INT_SRAM SIZE 1024
terom@1: ; #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
terom@1: 
terom@1: 
terom@1: 
terom@1: ; ***** BOOTLOADER DECLARATIONS ******************************************
terom@1: .equ	NRWW_START_ADDR	= 0x1c00
terom@1: .equ	NRWW_STOP_ADDR	= 0x1fff
terom@1: .equ	RWW_START_ADDR	= 0x0
terom@1: .equ	RWW_STOP_ADDR	= 0x1bff
terom@1: .equ	PAGESIZE	= 64
terom@1: .equ	FIRSTBOOTSTART	= 0x1f80
terom@1: .equ	SECONDBOOTSTART	= 0x1f00
terom@1: .equ	THIRDBOOTSTART	= 0x1e00
terom@1: .equ	FOURTHBOOTSTART	= 0x1c00
terom@1: .equ	SMALLBOOTSTART	= FIRSTBOOTSTART
terom@1: .equ	LARGEBOOTSTART	= FOURTHBOOTSTART
terom@1: 
terom@1: 
terom@1: 
terom@1: ; ***** INTERRUPT VECTORS ************************************************
terom@1: .equ	INT0addr	= 0x0002	; External Interrupt Request 0
terom@1: .equ	INT1addr	= 0x0004	; External Interrupt Request 1
terom@1: .equ	PCI0addr	= 0x0006	; Pin Change Interrupt Request 0
terom@1: .equ	PCI1addr	= 0x0008	; Pin Change Interrupt Request 0
terom@1: .equ	PCI2addr	= 0x000a	; Pin Change Interrupt Request 1
terom@1: .equ	WDTaddr	= 0x000c	; Watchdog Time-out Interrupt
terom@1: .equ	OC2Aaddr	= 0x000e	; Timer/Counter2 Compare Match A
terom@1: .equ	OC2Baddr	= 0x0010	; Timer/Counter2 Compare Match A
terom@1: .equ	OVF2addr	= 0x0012	; Timer/Counter2 Overflow
terom@1: .equ	ICP1addr	= 0x0014	; Timer/Counter1 Capture Event
terom@1: .equ	OC1Aaddr	= 0x0016	; Timer/Counter1 Compare Match A
terom@1: .equ	OC1Baddr	= 0x0018	; Timer/Counter1 Compare Match B
terom@1: .equ	OVF1addr	= 0x001a	; Timer/Counter1 Overflow
terom@1: .equ	OC0Aaddr	= 0x001c	; TimerCounter0 Compare Match A
terom@1: .equ	OC0Baddr	= 0x001e	; TimerCounter0 Compare Match B
terom@1: .equ	OVF0addr	= 0x0020	; Timer/Couner0 Overflow
terom@1: .equ	SPIaddr	= 0x0022	; SPI Serial Transfer Complete
terom@1: .equ	URXCaddr	= 0x0024	; USART Rx Complete
terom@1: .equ	UDREaddr	= 0x0026	; USART, Data Register Empty
terom@1: .equ	UTXCaddr	= 0x0028	; USART Tx Complete
terom@1: .equ	ADCCaddr	= 0x002a	; ADC Conversion Complete
terom@1: .equ	ERDYaddr	= 0x002c	; EEPROM Ready
terom@1: .equ	ACIaddr	= 0x002e	; Analog Comparator
terom@1: .equ	TWIaddr	= 0x0030	; Two-wire Serial Interface
terom@1: .equ	SPMRaddr	= 0x0032	; Store Program Memory Read
terom@1: 
terom@1: .equ	INT_VECTORS_SIZE	= 52	; size in words
terom@1: 
terom@1: ; #endif  /* _M168DEF_INC_ */
terom@1: 
terom@1: ; ***** END OF FILE ******************************************************