# HG changeset patch
# User Tero Marttila <terom@fixme.fi>
# Date 1273070010 -10800
# Node ID f7bdcc9806e67612abc66e112c5b0bb82b82e939
# Parent  e0b8d42c62e15593e68d06dbf46541046e4c8ba7
16-bit timer blink\!

diff -r e0b8d42c62e1 -r f7bdcc9806e6 hw.S
--- a/hw.S	Wed May 05 15:50:34 2010 +0300
+++ b/hw.S	Wed May 05 17:33:30 2010 +0300
@@ -3,19 +3,70 @@
 .list
 
 ; Interrupt vector
+.org 0x00
         rjmp        main            ; Reset
 
+.org OC1Aaddr
+        rjmp        timer           ; Timer 1 Compare A 
+
 ; Program code
 main:
-        ; Setup pins for output
-        sbi         DDRB,   PORTB4      ; Out
-        sbi         DDRB,   PORTB5      ; Out
+    ; Setup pins for output
+        sbi         DDRB, PORTB4        ; Out
+        sbi         DDRB, PORTB5        ; Out
+        
+    ; Flags for output
+        ldi         r16, (1 << PORTB4)
 
-        ; Activate
-        sbi         PORTB,  PORTB4      ; On
-        sbi         PORTB,  PORTB5      ; On
+    ; Setup Timer 0
+        ; Count to 64k
+        ldi         r18, HIGH(0xffff)
+        ldi         r19, LOW(0xffff)
+        sts         OCR1AH, r18
+        sts         OCR1AL, r19
+ 
+        ; Normal port operation for both comperators
+        ; Bits WGM10:1 zero
+        ldi         r18,    0x00
+        sts         TCCR1A, r18
+ 
+        ; CTC mode, 1/64 prescaled
+        ; the timer will start counting from now, but that shouldn't matter..
+        ldi         r18,    (1 << WGM12) | (0b011 << CS10)
+        sts         TCCR1B, r18
+       
+        ; Enable timer interrupt
+        ldi         r18, (1 << OCIE1A)
+        sts         TIMSK1, r18
+        
+        ; Setup sleep for Idle mode
+        ldi         r18, (0b000 << SM0) | (1 << SE)
+        sts         SMCR, r18
+
+        ; ...and enable interrupts
+        sei
 
 loop:
-        ; Stay and loop
-        rjmp        loop
+        ; Flip
+        com         r16
+        
+        ; Output
+        out         PORTB, r16
 
+        ; Wait
+wait:   sleep
+        cpi         r20, 1
+        brne        wait
+        ldi         r20, 0
+
+        ; continue
+        rjmp loop
+
+; Counter overflow handler
+timer:
+        ; Set flag
+        ldi         r20, 1
+
+        ; Re-enable interrupts
+        reti
+