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;*************************************************************************** 

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;* 

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;* "div8u" - 8/8 Bit Unsigned Division 

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;* 

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;* This subroutine divides the two register variables "dd8u" (dividend) and  

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;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in 

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;* "drem8u". 

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;*   

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;* Number of words	:14 

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;* Number of cycles	:97 

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;* Low registers used	:1 (drem8u) 

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;* High registers used  :3 (dres8u/dd8u,dv8u,dcnt8u) 

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;* 

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;*************************************************************************** 

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;***** Subroutine Register Variables 

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.def	drem8u	=r15		;remainder 

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.def	dres8u	=r16		;result 

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.def	dd8u	=r16		;dividend 

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.def	dv8u	=r17		;divisor 

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.def	dcnt8u	=r18		;loop counter 

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;***** Code 

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div8u:	sub	drem8u,drem8u	;clear remainder and carry 

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		ldi	dcnt8u,9		;init loop counter 

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d8u_1:	rol	dd8u			;shift left dividend 

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		dec	dcnt8u			;decrement counter 

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		brne	d8u_2		;if done 

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		ret					;    return 

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d8u_2:	rol	drem8u			;shift dividend into remainder 

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		sub	drem8u,dv8u		;remainder = remainder - divisor 

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		brcc	d8u_3		;if result negative 

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		add	drem8u,dv8u		;    restore remainder 

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		clc					;    clear carry to be shifted into result 

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		rjmp	d8u_1		;else 

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d8u_3:	sec					;    set carry to be shifted into result 

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		rjmp	d8u_1 

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