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;; vim: filetype=avr

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;;

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;; Timer unit control and use

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;;

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.equ TIMER_FLAGS = GPIOR0

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;; Timer0

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; Compare output mode

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.set TIMER0_COMA = 0b00			; null

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.set TIMER0_COMB = 0b00			; null

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; Waveform Generation Mode (triplet low/high)

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.set TIMER0_WGML = 0b10			; CTC

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.set TIMER0_WGMH = 0b0			; CTC

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; Clock Source

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.set TIMER0_CS = 0b101			; 1/1024

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;; Timer1

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; Waveform Generation Mode (nibble low/high)

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.set TIMER1_WGML = 0b00			; CTC

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.set TIMER1_WGMH = 0b01			; CTC

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; Clock Source

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.set TIMER1_CS = 0b101			; 1/1024

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; Flags

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.equ TIMER1_BUSY = 1

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.set SLEEP_MODE = 0b000			; Idle

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Timer_Init:

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Timer0_Init:

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		; OC0A/B disconnected from output

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		; No PWM mode

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		ldi			r16, (TIMER0_COMA << COM0A0) | (TIMER0_COMB << COM0B0) | (TIMER0_WGML << WGM00)

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		out			TCCR0A, r16

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		; Clear

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		ldi			r16, 0

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		out			OCR0A, r16

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		out			OCR0B, r16

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		out			TCCR0B, r16

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		; Enable compare interrupt

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		ldi			r16, (1 << OCIE0A)

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		sts			TIMSK0, r16

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Timer1_Init:

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		; OC1A/B disconnected from output

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		; No PWM mode

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		poke		[TCCR1A, r16, (0b00 << COM1A0) | (0b00 << COM1B0) | (TIMER1_WGML << WGM10)]

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		; Clear

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		poke		[TCCR1B, r16, 0]

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		poke		[TCCR1C, r16, 0]

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		; Enable compare interrupt

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		poke		[TIMSK1, r16, (1 << OCIE1A)]

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Sleep_init:

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		; Select sleep mode

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		; Enable `sleep`

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		poke		[SMCR, r16, (SLEEP_MODE << SM0) | (1 << SE)]

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		; Disable ADC

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		poke		[SMCR, r16, (1 << PRTWI) | (1 << PRUSART0) | (1 << PRADC)]

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		ret

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;; Timer0 is recurring; this starts it running, and it keeps hitting OC0A periodically

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;;  Input: r16 (period, in 1k-cycles)

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Timer0_Start:

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	; Initialize timer

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		; set CTC trigger from r16

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		out			OCR0A, r16

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		; clear counter

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		ldi			r16, 0

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		out			TCNT0, r16

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	; Start

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		; WGM

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		; Clock Source

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		ldi			r16, (TIMER0_WGMH << WGM02) | (TIMER0_CS << CS00)

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		out			TCCR0B, r16

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		ret

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Timer0_Read8:

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		in			r16, TCNT0

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		ret

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;; Timer0 Compare A interrupt handler

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Timer_OC0A:

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		in			r0, SREG

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		; Run callback

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		rcall		TIMER0_CB_A

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		out			SREG, r0

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		reti

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;; Timer1 is one-shot; this starts it running, and it is then stopped once it hits OC1A

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Timer1_Start:

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	; Initialize timer

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		poke		[TCNT1H, r16, high(0)]

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		poke		[TCNT1L, r16, low(0)]

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	; Set flag

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		sbi			TIMER_FLAGS, TIMER1_BUSY

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	; Start

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		; WGM

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		; Clock Source

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		poke		[TCCR1B, r16, (TIMER1_WGMH << WGM12) | (TIMER1_CS << CS10)]

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		ret

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Timer1_Stop:

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		; WGM

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		; Clock off

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		poke		[TCCR1B, r16, (TIMER1_WGMH << WGM12) | (0b00 << CS10)]

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	; Clear flag

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		cbi			TIMER_FLAGS, TIMER1_BUSY

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		ret

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;; Timer1 Compare A interrupt handler

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Timer_OC1A:

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		in			r0, SREG

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	; Stop timer

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		rcall		Timer1_Stop

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		out			SREG, r0

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		reti

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;; Prime the timer and sleep for 1s

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Timer_Sleep_1s:

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	; Initialize counter to 16k cycles

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		ldi			XH, high(16 * 1024)

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		ldi			XL, low(16 * 1024)

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	;; Continue

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;; Count to X

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Timer_Sleep:

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	; Set TOP

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		sts			OCR1AH, XH

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		sts			OCR1AL, XL

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	; Start timer

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		rcall		Timer1_Start

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	; Wait for timer to complete

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_timer1_sleep:

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		sleep

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		sbic		TIMER_FLAGS, TIMER1_BUSY

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		rjmp		_timer1_sleep

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	; Done

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		ret

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;; Update timer for given timeout

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Timer_Update:

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	; Set TOP

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		sts			OCR1AH, XH

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		sts			OCR1AL, XL

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	; Check timer

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		lds			YL, TCNT1L

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		lds			YH, TCNT1H

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		cp			YL, XL

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		cpc			YH, XH

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		brlo		timer_up_out

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	; Update

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	; XXX: figure out a better way to do this...

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		ldi			r16, 0

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		subi		XL, 2

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		sbc			XH, r16

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		sts			TCNT1L, XL

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		sts			TCNT1H, XH

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timer_up_out:

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	; Done

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		ret

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