55
|
1 |
#define SPI_DDR DDRB
|
|
2 |
#define SPI_PORT PORTB
|
|
3 |
|
|
4 |
#define SPI_SCK PORTB5
|
|
5 |
#define SPI_MISO PORTB4
|
|
6 |
#define SPI_MOSI PORTB3
|
|
7 |
#define SPI_SS PORTB2
|
|
8 |
|
|
9 |
/* State */
|
|
10 |
#define SPI_COUNT 1
|
|
11 |
|
|
12 |
static char spi_rx[SPI_COUNT], spi_tx[SPI_COUNT];
|
|
13 |
|
|
14 |
enum {
|
|
15 |
SPI_DORD_MSB = 0b0,
|
|
16 |
|
|
17 |
SPI_DORD = SPI_DORD_MSB
|
|
18 |
};
|
|
19 |
|
|
20 |
enum {
|
|
21 |
SPI_CPOL_RISING = 0b0,
|
|
22 |
|
|
23 |
SPI_CPOL = SPI_CPOL_RISING
|
|
24 |
};
|
|
25 |
|
|
26 |
enum {
|
|
27 |
SPI_CPHA_SAMPLE = 0b0,
|
|
28 |
|
|
29 |
SPI_CPHA = SPI_CPHA_SAMPLE
|
|
30 |
};
|
|
31 |
|
|
32 |
enum {
|
|
33 |
SPI_CLOCK_4 = 0b000,
|
|
34 |
SPI_CLOCK_16 = 0b001,
|
|
35 |
SPI_CLOCK_64 = 0b010,
|
|
36 |
SPI_CLOCK_128 = 0b011,
|
|
37 |
|
|
38 |
SPI_CLOCK = SPI_CLOCK_16
|
|
39 |
};
|
|
40 |
|
|
41 |
/*
|
|
42 |
* Initialize in SPI master mode.
|
|
43 |
*/
|
|
44 |
void spi_init ()
|
|
45 |
{
|
|
46 |
// set output modes
|
|
47 |
sbi(&SPI_DDR, SPI_SCK); // out
|
|
48 |
sbi(&SPI_DDR, SPI_MOSI); // out
|
|
49 |
sbi(&SPI_DDR, SPI_SS); // out
|
|
50 |
|
|
51 |
// initialize bus
|
|
52 |
sbi(&SPI_PORT, SPI_SS); // high (off)
|
|
53 |
|
|
54 |
// set mode
|
|
55 |
SPCR = (
|
|
56 |
// SPI Interrupt Enable
|
|
57 |
(0b0 << SPIE) // disable
|
|
58 |
|
|
59 |
// SPI Enable
|
|
60 |
| (0b1 << SPE) // enable
|
|
61 |
|
|
62 |
// Data Order
|
|
63 |
| (SPI_DORD << DORD)
|
|
64 |
|
|
65 |
// Master/Slave Select
|
|
66 |
| (0b1 << MSTR) // master
|
|
67 |
|
|
68 |
// Clock Polarity
|
|
69 |
| (SPI_CPOL << CPOL)
|
|
70 |
|
|
71 |
// Clock Phase
|
|
72 |
| (SPI_CPHA << CPHA)
|
|
73 |
|
|
74 |
// SPI Clock Rate Select
|
|
75 |
| ((SPI_CLOCK & 0b11) << SPR0)
|
|
76 |
);
|
|
77 |
SPSR = (
|
|
78 |
(((SPI_CLOCK & 0b100) >> 2) << SPI2X)
|
|
79 |
);
|
|
80 |
}
|
|
81 |
|
|
82 |
/*
|
|
83 |
* Perform an SPI bus update.
|
|
84 |
*/
|
|
85 |
void spi_update ()
|
|
86 |
{
|
|
87 |
char i;
|
|
88 |
char *rx = spi_rx + SPI_COUNT, *tx = spi_tx + SPI_COUNT;
|
|
89 |
|
|
90 |
// start of packet
|
|
91 |
cbi(&SPI_PORT, SPI_SS); // low
|
|
92 |
|
|
93 |
for (i = SPI_COUNT; i > 0; i--) {
|
|
94 |
// out
|
|
95 |
SPDR = *--tx;
|
|
96 |
|
|
97 |
// sync
|
|
98 |
while (!tbi(&SPSR, SPIF))
|
|
99 |
;
|
|
100 |
|
|
101 |
*--rx = SPDR;
|
|
102 |
}
|
|
103 |
|
|
104 |
// end of packet
|
|
105 |
sbi(&SPI_PORT, SPI_SS); // high
|
|
106 |
}
|