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#define SPI_DDR     DDRB

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#define SPI_PORT    PORTB

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#define SPI_SCK     PORTB5

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#define SPI_MISO    PORTB4

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#define SPI_MOSI    PORTB3

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#define SPI_SS      PORTB2

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/* State */

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#define SPI_COUNT   2

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static char spi_rx[SPI_COUNT], spi_tx[SPI_COUNT];

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enum {

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    SPI_DORD_MSB        = 0b0,

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    SPI_DORD            = SPI_DORD_MSB

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};

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enum {

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    SPI_CPOL_RISING     = 0b0,

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    SPI_CPOL            = SPI_CPOL_RISING

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};

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enum {

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    SPI_CPHA_SAMPLE     = 0b0,

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    SPI_CPHA            = SPI_CPHA_SAMPLE

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};

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enum {

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    SPI_CLOCK_4         = 0b000,

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    SPI_CLOCK_16        = 0b001,

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    SPI_CLOCK_64        = 0b010,

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    SPI_CLOCK_128       = 0b011,

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    SPI_CLOCK           = SPI_CLOCK_16

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};

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/*

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 * Initialize in SPI master mode.

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 */

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void spi_init ()

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{

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    // set output modes

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    sbi(&SPI_DDR, SPI_SCK);     // out

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    sbi(&SPI_DDR, SPI_MOSI);    // out

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    sbi(&SPI_DDR, SPI_SS);      // out

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    // initialize bus

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    sbi(&SPI_PORT, SPI_SS);     // high (off)

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    // set mode

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    SPCR = (

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            // SPI Interrupt Enable

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            (0b0 << SPIE) // disable

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            // SPI Enable

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        |   (0b1 << SPE) // enable

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            // Data Order

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        |   (SPI_DORD << DORD)

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            // Master/Slave Select

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        |   (0b1 << MSTR) // master

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            // Clock Polarity

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        |   (SPI_CPOL << CPOL)

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            // Clock Phase

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        |   (SPI_CPHA << CPHA)

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            // SPI Clock Rate Select

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        |   ((SPI_CLOCK & 0b11) << SPR0)

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    );

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    SPSR = (

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            (((SPI_CLOCK & 0b100) >> 2) << SPI2X)

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    );

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}

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/*

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 * Perform an SPI bus update.

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 */

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void spi_update ()

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{

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    char i;

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    char *rx = spi_rx + SPI_COUNT, *tx = spi_tx + SPI_COUNT;

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    // start of packet

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    cbi(&SPI_PORT, SPI_SS); // low

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    for (i = SPI_COUNT; i > 0; i--) {

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        // out

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        SPDR = *--tx;

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        // sync

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        while (!tbi(&SPSR, SPIF))

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            ;

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        *--rx = SPDR;

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    }

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    // end of packet

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    sbi(&SPI_PORT, SPI_SS); // high

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}