qmsk-dmx: timer.inc@51344df466ca (annotated)

18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	1	;; vim: filetype=avr
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	2	;;
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	3	;; Timer unit control and use
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	4	;;
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	5
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	6	; Waveform Generation Mode (nibble low/high)
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	7	.set TIMER_WGML = 0b00
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	8	.set TIMER_WGMH = 0b01
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	9
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	10	; Clock Source
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	11	.set TIMER_CS = 0b101
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	12
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	13	.equ TIMER_FLAGS = GPIOR0
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	14	.equ TIMER_BUSY = 1
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	15
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	16	.set SLEEP_MODE = 0b000 ; Idle
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	17
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	18	Timer_Init:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	19	; OC1A/B disconnected from output
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	20	; No PWM mode
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	21	poke [TCCR1A, r16, (0b00 << COM1A0) \| (0b00 << COM1B0) \| (TIMER_WGML << WGM10)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	22
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	23	; Clear
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	24	poke [TCCR1B, r16, 0]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	25	poke [TCCR1C, r16, 0]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	26
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	27	; Enable timer overflow interrupt
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	28	poke [TIMSK1, r16, (1 << OCIE1A)]
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	29
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	30	Sleep_init:
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	31	; Select sleep mode
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	32	; Enable `sleep`
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	33	poke [SMCR, r16, (SLEEP_MODE << SM0) \| (1 << SE)]
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	34
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	35	; Disable ADC
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	36	poke [SMCR, r16, (1 << PRTWI) \| (1 << PRUSART0) \| (1 << PRADC)]
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	37
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	38	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	39
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	40	Timer_Start:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	41	; Initialize timer
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	42	poke [TCNT1H, r16, high(0)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	43	poke [TCNT1L, r16, low(0)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	44
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	45	; Set flag
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	46	sbi TIMER_FLAGS, TIMER_BUSY
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	47
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	48	; WGM
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	49	; Clock Source
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	50	poke [TCCR1B, r16, (TIMER_WGMH << WGM12) \| (TIMER_CS << CS10)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	51
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	52	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	53
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	54	Timer_Stop:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	55	; WGM
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	56	; Clock off
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	57	poke [TCCR1B, r16, (TIMER_WGMH << WGM12) \| (0b00 << CS10)]
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	58
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	59	; Clear flag
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	60	cbi TIMER_FLAGS, TIMER_BUSY
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	61
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	62	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	63
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	64	;; Timer Compare 1A interrupt handler
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	65	Timer_OC1A:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	66	in r0, SREG
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	67
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	68	; Stop timer
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	69	rcall Timer_Stop
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	70
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	71	out SREG, r0
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	72	reti
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	73
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	74	;; Count to X
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	75	Timer_Sleep:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	76	; Set TOP
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	77	sts OCR1AH, XH
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	78	sts OCR1AL, XL
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	79
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	80	; Start timer
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	81	rcall Timer_Start
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	82
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	83	; Wait for timer to complete
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	84	_timer_sleep:
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	85	sleep
95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	86
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	87	sbic TIMER_FLAGS, TIMER_BUSY
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	88	rjmp _timer_sleep
21 95549ce0e3da timer: try and actually sleep Tero Marttila <terom@fixme.fi> parents: 18 diff changeset	89
18 79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	90	; Done
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	91	ret
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	92
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	93	;; Prime the timer and sleep for 1s
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	94	Timer_Sleep_1s:
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	95	; Initialize counter to 16k cycles
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	96	ldi XH, high(16 * 1024)
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	97	ldi XL, low(16 * 1024)
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	98
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	99	; Start timer
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	100	rjmp Timer_Sleep
79b25e81721f use timer for 1s delay Tero Marttila <terom@fixme.fi> parents: diff changeset	101

author	Tero Marttila <terom@fixme.fi>
	Sat, 08 May 2010 21:27:44 +0300
changeset 28	51344df466ca
parent 21	95549ce0e3da
child 29	453550e69e07
permissions	-rw-r--r--