| author | Tero Marttila <terom@fixme.fi> |
| Sat, 08 May 2010 21:19:53 +0300 | |
| changeset 26 | db2ec641c955 |
| parent 24 | 8100038e3d58 |
| child 30 | 5226e512755c |
| permissions | -rw-r--r-- |
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17
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
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parents:
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|
1 |
;; vim: filetype=avr |
| 18 | 2 |
;; |
3 |
;; SPI interface control and use |
|
4 |
;; |
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parents:
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5 |
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parents:
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6 |
.equ SPI_DDR = DDRB |
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a7c668003a19
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parents:
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|
7 |
.equ SPI_PORT = PORTB |
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a7c668003a19
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parents:
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8 |
.equ SPI_SCK = PORTB5 |
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a7c668003a19
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parents:
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9 |
.equ SPI_MISO = PORTB4 |
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a7c668003a19
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parents:
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10 |
.equ SPI_MOSI = PORTB3 |
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a7c668003a19
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parents:
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11 |
.equ SPI_SS = PORTB2 |
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a7c668003a19
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parents:
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12 |
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a7c668003a19
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parents:
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13 |
.equ SPI_FLAGS = GPIOR0 |
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a7c668003a19
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parents:
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14 |
.equ SPI_BUSY = 0 |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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15 |
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26
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16 |
; Number of in/out bytes |
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db2ec641c955
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17 |
.set SPI_BUFLEN = 2 |
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18 |
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19 |
.dseg |
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20 |
spi_inbuf: .byte SPI_BUFLEN |
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21 |
spi_outbuf: .byte SPI_BUFLEN |
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22 |
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23 |
.cseg |
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24 |
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17
a7c668003a19
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parents:
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25 |
;; Initialize SPI subsystem for master operation |
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a7c668003a19
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parents:
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26 |
SPI_Init: |
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a7c668003a19
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parents:
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27 |
; Set modes |
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a7c668003a19
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parents:
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28 |
sbi SPI_DDR, SPI_SCK ; Out |
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a7c668003a19
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parents:
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29 |
sbi SPI_DDR, SPI_MOSI ; Out |
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parents:
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30 |
sbi SPI_DDR, SPI_SS ; Out |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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31 |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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32 |
; Drive SS high (off) |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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33 |
sbi SPI_PORT, SPI_SS |
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parents:
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34 |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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35 |
; Set control mode |
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36 |
; XXX: Enable interrupt |
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parents:
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37 |
; Enable SPI |
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a7c668003a19
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parents:
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38 |
; MSB first |
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a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
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39 |
; Master mode |
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a7c668003a19
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parents:
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40 |
; Polarity/phase: Mode 0 (sample on rising edge) |
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; Clock rate 1/16 |
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42 |
ldi r16, (0 << SPIE) | (1 << SPE) | (0 << DORD) | (1 << MSTR) | (0 << CPOL) | (0 << CPHA) | (0b01 << SPR0) |
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43 |
out SPCR, r16 |
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a7c668003a19
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parents:
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44 |
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a7c668003a19
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parents:
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45 |
; Flags |
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a7c668003a19
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parents:
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46 |
clr r0 |
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a7c668003a19
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parents:
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47 |
out SPI_FLAGS, r0 |
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a7c668003a19
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parents:
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48 |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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49 |
; Done |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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50 |
ret |
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a7c668003a19
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parents:
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51 |
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52 |
;; Send/Recv from/to SPI buffers |
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parents:
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53 |
SPI_SendRecv: |
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parents:
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54 |
; Flag |
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a7c668003a19
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Tero Marttila <terom@fixme.fi>
parents:
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55 |
sbi SPI_FLAGS, SPI_BUSY |
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a7c668003a19
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parents:
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56 |
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57 |
; Start of packet |
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parents:
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58 |
cbi SPI_PORT, SPI_SS |
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parents:
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59 |
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60 |
; Init buffers |
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61 |
ldi r16, SPI_BUFLEN |
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62 |
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63 |
; send/recv in reverse order |
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db2ec641c955
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64 |
ldi XL, low(spi_inbuf + SPI_BUFLEN) |
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65 |
ldi XH, high(spi_inbuf + SPI_BUFLEN) |
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66 |
ldi YL, low(spi_outbuf + SPI_BUFLEN) |
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67 |
ldi YH, high(spi_outbuf + SPI_BUFLEN) |
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68 |
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69 |
; Write |
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70 |
spi_sr_next: |
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71 |
; load+send tail byte |
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72 |
ld r1, -Y |
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73 |
out SPDR, r1 |
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74 |
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75 |
; Wait |
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76 |
spi_sr_wait: |
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77 |
in r1, SPSR |
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78 |
sbrs r1, SPIF |
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79 |
rjmp spi_sr_wait |
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80 |
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81 |
; Read |
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82 |
; read+store tail byte |
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83 |
in r1, SPDR |
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84 |
st -X, r1 |
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85 |
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86 |
; Done? |
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87 |
dec r16 |
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88 |
brne spi_sr_next ; if nonzero |
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89 |
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90 |
; End of packet |
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91 |
sbi SPI_PORT, SPI_SS |
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92 |
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parents:
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|
93 |
; Done |
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parents:
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94 |
ret |
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parents:
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95 |
|
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parents:
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|
96 |
;; Service SPI interrupt |
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parents:
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|
97 |
SPI_Interrupt: |
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98 |
; XXX: disabled |
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parents:
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99 |
reti |
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parents:
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100 |
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parents:
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101 |