author | Tero Marttila <terom@fixme.fi> |
Sat, 08 May 2010 20:58:32 +0300 | |
changeset 24 | 8100038e3d58 |
parent 23 | a6afc0eb347f |
child 26 | db2ec641c955 |
permissions | -rw-r--r-- |
17
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|
1 |
;; vim: filetype=avr |
18 | 2 |
;; |
3 |
;; SPI interface control and use |
|
4 |
;; |
|
17
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parents:
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|
5 |
|
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parents:
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6 |
.equ SPI_DDR = DDRB |
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7 |
.equ SPI_PORT = PORTB |
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8 |
.equ SPI_SCK = PORTB5 |
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9 |
.equ SPI_MISO = PORTB4 |
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10 |
.equ SPI_MOSI = PORTB3 |
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11 |
.equ SPI_SS = PORTB2 |
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parents:
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12 |
|
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13 |
.equ SPI_FLAGS = GPIOR0 |
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14 |
.equ SPI_BUSY = 0 |
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parents:
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15 |
|
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parents:
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16 |
;; Initialize SPI subsystem for master operation |
a7c668003a19
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17 |
SPI_Init: |
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18 |
; Set modes |
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19 |
sbi SPI_DDR, SPI_SCK ; Out |
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20 |
sbi SPI_DDR, SPI_MOSI ; Out |
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parents:
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21 |
sbi SPI_DDR, SPI_SS ; Out |
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22 |
|
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parents:
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23 |
; Drive SS high (off) |
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24 |
sbi SPI_PORT, SPI_SS |
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25 |
|
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26 |
; Set control mode |
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27 |
; XXX: Enable interrupt |
17
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28 |
; Enable SPI |
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29 |
; MSB first |
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30 |
; Master mode |
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31 |
; Polarity/phase: Mode 0 (sample on rising edge) |
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32 |
; Clock rate 1/16 |
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33 |
ldi r16, (0 << SPIE) | (1 << SPE) | (0 << DORD) | (1 << MSTR) | (0 << CPOL) | (0 << CPHA) | (0b01 << SPR0) |
17
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34 |
out SPCR, r16 |
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35 |
|
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36 |
; Flags |
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37 |
clr r0 |
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38 |
out SPI_FLAGS, r0 |
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39 |
|
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40 |
; Done |
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41 |
ret |
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42 |
|
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43 |
;; Send/recv one byte |
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44 |
;; Input: r16 |
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45 |
;; Output: r10 |
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46 |
;; Note: should not be busy... |
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47 |
SPI_SendRecv: |
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48 |
; Flag |
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49 |
sbi SPI_FLAGS, SPI_BUSY |
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50 |
|
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51 |
; Enable slave (low) |
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52 |
cbi SPI_PORT, SPI_SS |
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53 |
|
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54 |
; Write byte (starts SCK) |
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55 |
out SPDR, r16 |
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56 |
|
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57 |
; Wait for byte to be sent |
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58 |
spi_sr_wait: |
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59 |
in r1, SPSR |
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60 |
sbrs r1, SPIF |
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61 |
rjmp spi_sr_wait |
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62 |
|
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63 |
; Read |
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64 |
mov r10, r11 |
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65 |
in r11, SPDR |
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66 |
|
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67 |
; Drive SS high (end of packet) |
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68 |
sbi SPI_PORT, SPI_SS |
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69 |
|
17
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70 |
; Done |
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71 |
ret |
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72 |
|
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73 |
;; Send buffer bytes |
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74 |
;; Input: post-buffer byte in X, buffer length in r16 |
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75 |
;; Output: r10 |
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76 |
;; Note: should not be busy... |
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77 |
SPI_SendBuf: |
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78 |
; Flag |
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79 |
sbi SPI_FLAGS, SPI_BUSY |
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80 |
|
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81 |
; Enable slave (low) |
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82 |
cbi SPI_PORT, SPI_SS |
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83 |
|
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84 |
; Write byte from X (starts SCK) |
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85 |
spi_srb_next: |
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86 |
ld r1, -X |
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87 |
out SPDR, r1 |
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88 |
|
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89 |
; Wait for byte to be sent |
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90 |
spi_srb_wait: |
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91 |
in r1, SPSR |
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92 |
sbrs r1, SPIF |
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93 |
rjmp spi_srb_wait |
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94 |
|
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95 |
; Read |
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96 |
mov r10, r11 |
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97 |
in r11, SPDR |
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98 |
|
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99 |
; Done? |
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100 |
dec r16 |
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101 |
brne spi_srb_next |
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102 |
|
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103 |
; Drive SS high (end of packet) |
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104 |
sbi SPI_PORT, SPI_SS |
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105 |
|
17
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106 |
; Done |
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107 |
ret |
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
108 |
|
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
109 |
;; Service SPI interrupt |
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
110 |
SPI_Interrupt: |
23
a6afc0eb347f
synchronous SPI, two-digit led7
Tero Marttila <terom@fixme.fi>
parents:
18
diff
changeset
|
111 |
; XXX: disabled |
17
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
112 |
reti |
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
113 |
|
a7c668003a19
split led7seg.s into .inc modules, and update Makefile to use .s -> .hex, and above .inc's for led7seg
Tero Marttila <terom@fixme.fi>
parents:
diff
changeset
|
114 |