spi.inc
author Tero Marttila <terom@paivola.fi>
Sun, 20 Apr 2014 23:51:57 +0300
changeset 80 5254ba612630
parent 36 06e1e554acbb
permissions -rw-r--r--
dmx-web: slightly better RGB colorpicker control..
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;; vim: filetype=avr
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;;
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;; SPI interface control and use
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;;
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;; I/O Port
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.equ SPI_DDR    = DDRB
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.equ SPI_PORT   = PORTB
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.equ SPI_SCK    = PORTB5
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.equ SPI_MISO   = PORTB4
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.equ SPI_MOSI   = PORTB3
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.equ SPI_SS     = PORTB2
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;; Internal status flags
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.equ SPI_FLAGS  = GPIOR0
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.equ SPI_BUSY   = 0
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;; Settings
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.set SPI_DORD = 0           ; word order
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.set SPI_CPOL = 0           ; clock polarity
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.set SPI_CPHA = 0           ; clock phase
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.set SPI_CLOCK  = 0b01      ; clock speed
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;; Internal state
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; Number of in/out bytes
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.set SPI_BUFLEN  = 2
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.dseg
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; Buffer for incoming frames
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spi_inbuf:  .byte SPI_BUFLEN
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; Buffer for outgoing frames
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spi_outbuf: .byte SPI_BUFLEN
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.cseg
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;; Initialize SPI subsystem for master operation
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SPI_Init:
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    ; Set modes
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        sbi         SPI_DDR, SPI_SCK        ; Out
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        sbi         SPI_DDR, SPI_MOSI       ; Out
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        sbi         SPI_DDR, SPI_SS         ; Out
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    ; Drive SS high (off)
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        sbi         SPI_PORT, SPI_SS
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    ; Set control mode
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        ; XXX: Enable interrupt
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        ; Enable SPI
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        ; MSB first
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        ; Master mode
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        ; Polarity/phase: Mode 0 (sample on rising edge)
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        ; Clock rate 1/16
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        ldi         r16, (0 << SPIE) | (1 << SPE) | (SPI_DORD << DORD) | (1 << MSTR) | (SPI_CPOL << CPOL) | (SPI_CPHA << CPHA) | (SPI_CLOCK << SPR0)
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        out         SPCR, r16
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    ; Flags
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        clr         r0
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        out         SPI_FLAGS, r0
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    ; Start update timer
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    ; XXX: also used for ADC
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;        ldi         r16, 64         ; every 64k cycles
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;        rcall       Timer0_Start
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    ; Done
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        ret
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;; Triggered by Timer0, updates the spi_bufs
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;;  Run from timer interrupt context
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SPI_Update:
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        ; skip if updating
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        sbic        SPI_FLAGS, SPI_BUSY
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        ret
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    ;; Continue
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    ; XXX: blocks too much?
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;; Send/Recv from/to SPI buffers
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SPI_SendRecv:
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    ; Flag
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        sbi         SPI_FLAGS, SPI_BUSY
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    ; Start of packet
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        cbi         SPI_PORT, SPI_SS
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    ; Init buffers
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        ldi         r16, SPI_BUFLEN
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        ; send/recv in reverse order
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        ldi         XL, low(spi_inbuf + SPI_BUFLEN)
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        ldi         XH, high(spi_inbuf + SPI_BUFLEN)
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        ldi         YL, low(spi_outbuf + SPI_BUFLEN)
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        ldi         YH, high(spi_outbuf + SPI_BUFLEN)
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    ; Write
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spi_sr_next:
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        ; load+send tail byte
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        ld          r1, -Y
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        out         SPDR, r1
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    ; Wait
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spi_sr_wait:        
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        in          r1, SPSR
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        sbrs        r1, SPIF
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        rjmp        spi_sr_wait
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    ; Read
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        ; XXX: wrong, should be head byte?
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        ; read+store tail byte
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        in          r1, SPDR
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        st          -X, r1
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    ; Done?
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        dec         r16
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        brne        spi_sr_next         ; if nonzero
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    ; End of packet
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        sbi         SPI_PORT, SPI_SS
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        cbi         SPI_FLAGS, SPI_BUSY
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    ; Done
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        ret
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33
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;; Wait for SPI to be ready for send
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SPI_Wait:
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    ; Test
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        in          r1, SPSR
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        sbrs        r1, SPIF
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        rjmp        SPI_Wait
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    ; Read SPDR to clear SPIF
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        in          r10, SPDR
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    ; Done
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        ret
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;; Service SPI interrupt
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SPI_Interrupt:
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    ; XXX: disabled
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        reti
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